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IR1153S

FIXED 22.2kHz FREQUENCY, µPFC ONE CYCLE CONTROL IC WITH BROWN-OUT PROTECTION

International Rectifier 

IR1153S

IR1153 General Description

The μPFC IR1153 IC is intended for power factor

correction in continuous conduction mode Boost PFC

converters operating at fixed switching frequency with

average current mode control. The IC operates based

on IR's proprietary "One Cycle Control" (OCC) PFC

algorithm based on the concept of resettable

integrator.

Theory of Operation

The OCC algorithm based on the resettable integrator

concept works using two loops - a slow outer voltage

loop and a fast inner current loop. The outer voltage

loop monitors the VFB pin and generates an error

signal which controls the amplitude of the input current

admitted into the PFC converter. In this way, the outer

voltage loop maintains output voltage regulation. The

voltage loop bandwidth is kept low enough to not track

the 2xfAC ripple in the output voltage and thus

generates an almost DC error signal under steady

state conditions.

The inner current loop maintains the sinusoidal profile

of the input current and thus is responsible for power

factor correction. The information about the sinusoidal

variation in input voltage is inherently available in the

input line current (or boost inductor current). Thus

there is no need to sense the input voltage to

generate a current reference. The current loop

employs the boost inductor current information to

generate PWM signals with a proportional sinusoidal

variation. This controls the shape of the input current

to be proportional to and in phase with the input

voltage. Average current mode operation is envisaged

by filtering the switching frequency ripple from the

current sense signal using an appropriately sized on-

chip RC filter. This filter also contributes to the

bandwidth of the current control loop. Thus the filter

bandwidth has to be high enough to track the 120Hz

rectified, sinusoidal current waveform and also filter

out the switching frequency ripple in the inductor

current. In IR1153 this averaging function can

effectively filter high ripple current ratios (as high as

40% at maximum input current) to accommodate

designs with small boost inductances.

The IC determines the boost converter instantaneous

duty cycle based on the resettable integrator concept.

The required signals are the voltage feedback loop

error signal Vm (which is the VCOMP pin voltage minus a

DC offset of VCOMP,START) and the current sense signal

VISNS. The resettable integrator generates a cycle-by-

cycle, saw-tooth signal called the PWM Ramp which

has an amplitude Vm and period 1/fSW hence a slope of

Vm*fSW.

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The current sense signal is amplified by the current

amplifier by a factor gDC and fed into the summing

node where it is subtracted from Vm to generate the

summer voltage (= Vm–gDC*VISNS). The summer

voltage is compared with the PWM ramp by the

PWM comparator of the IC to determine the gate

drive duty cycle. The instantaneous duty is

mathematically given by:

D = (Vm - gDC.VISNS)/Vm

Assuming steady state condition where the voltage

feedback loop is well regulated (Vm & VOUT are DC

signals) & hence instantaneous duty cycle follows

the boost-converter equation (D = 1 – VIN(t)/VOUT),

the control equation can be re-written as:

Vm = gDC.VISNS/(VIN(t)/VOUT)

Further, recognizing that VISNS = IL(t).RSNS and re-

arranging yields:

gDC.IL(t).RSNS = VmVIN(t)/VOUT

Since Vm, VOUT & gDC are constant terms:

IL(t) α VIN(t)

Thus the inductor current follows the input voltage

waveform & by definition power factor correction is

achieved.

Feature set

Fixed Frequency Operation

The IC is programmed to operate at a fixed

frequency of 22.2kHz (Typ). Internalization of the

oscillator offers excellent noise immunity even in

the noisy PFC environment while integration of the

oscillator into the OCC core of the IC eliminates

need for digital calibration circuits. Both these

factors render the gate drive jitter free thus

contributing to elimination of audible noise in PFC

magnetics.

IC Supply Circuit & Low start-up current

The IR1153 UVLO circuit maintains the IC in UVLO

mode during start-up if VCC pin voltage is less than

the VCC turn-on threshold, VCC,ON and current

consumption is less than 75uA. Should VCC pin

voltage should drop below VCC,UVLO during normal

operation, the IC is pushed back into UVLO mode

and VCC pin has to exceed VCC,ON again for normal

operation. There is no internal voltage clamping of

the VCC pin.

User initiated Micropower Sleep mode

The IC can be actively pushed into a micropower

Sleep Mode where current consumption is less

than 75uA by pulling OVP/EN pin below the Sleep

threshold, VSLEEP even while VCC is above VCC,ON.

This allows the user to disable PFC during

application stand-by situations in order to meet

stand-by regulations. Since VSLEEP is less than 1V,

even logic level signals can be employed.

© 2011 International Rectifier

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