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INTEL386

Intel386 SX MICROPROCESSOR

Intel 

Intel386TM SX MICROPROCESSOR

2 7 Interrupts and Exceptions

Interrupts and exceptions alter the normal program

flow in order to handle external events report errors

or exceptional conditions The difference between

interrupts and exceptions is that interrupts are used

to handle asynchronous external events while ex-

ceptions handle instruction faults Although a pro-

gram can generate a software interrupt via an INT N

instruction the processor treats software interrupts

as exceptions

Hardware interrupts occur as the result of an exter-

nal event and are classified into two types maskable

or non-maskable Interrupts are serviced after the

execution of the current instruction After the inter-

rupt handler is finished servicing the interrupt exe-

cution proceeds with the instruction immediately

after the interrupted instruction

Exceptions are classified as faults traps or aborts

depending on the way they are reported and wheth-

er or not restart of the instruction causing the excep-

tion is supported Faults are exceptions that are de-

tected and serviced before the execution of the

faulting instruction Traps are exceptions that are

reported immediately after the execution of the in-

struction which caused the problem Aborts are ex-

ceptions which do not permit the precise location of

the instruction causing the exception to be deter-

mined

Thus when an interrupt service routine has been

completed execution proceeds from the instruction

immediately following the interrupted instruction On

the other hand the return address from an excep-

tion fault routine will always point to the instruction

causing the exception and will include any leading

instruction prefixes Table 2 5 summarizes the possi-

ble interrupts for the Intel386 SX Microprocessor

and shows where the return address points to

Table 2 5 Interrupt Vector Assignments

Function

Interrupt

Number

Instruction Which

Can Cause

Exception

Return Address

Points to

Faulting

Instruction

Type

Divide Error

0 DIV IDIV

YES

FAULT

Debug Exception

1 any instruction

YES

TRAP

NMI Interrupt

2 INT 2 or NMI

NO

NMI

One Byte Interrupt

3 INT

NO

TRAP

Interrupt on Overflow

4 INTO

NO

TRAP

Array Bounds Check

5 BOUND

YES

FAULT

Invalid OP-Code

6 Any illegal instruction

YES

FAULT

Device Not Available

7 ESC WAIT

YES

FAULT

Double Fault

8

Any instruction that can

generate an exception

ABORT

Coprocessor Segment Overrun

9 ESC

NO

ABORT

Invalid TSS

10 JMP CALL IRET INT

YES

FAULT

Segment Not Present

11 Segment Register Instructions

YES

FAULT

Stack Fault

12 Stack References

YES

FAULT

General Protection Fault

13 Any Memory Reference

YES

FAULT

Page Fault

14 Any Memory Access or Code Fetch

YES

FAULT

Coprocessor Error

16 ESC WAIT

YES

FAULT

Intel Reserved

17 – 32

Two Byte Interrupt

33–255 INT n

NO

Some debug exceptions may report both traps on the previous instruction and faults on the next instruction

TRAP

17

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