MH64S72VJG Ver la hoja de datos (PDF) - MITSUBISHI ELECTRIC
Número de pieza
componentes Descripción
Fabricante
MH64S72VJG
MITSUBISHI ELECTRIC
MH64S72VJG Datasheet PDF : 57 Pages
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64S72VJG-5,-6
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN FUNCTION
CK0
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
CKE0
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S0,2
/RAS,/CAS,/W
A0-12
BA0-1
DQ0-63
CB0-7
DQM0-7
Vdd,Vs s
REGE
Input
Chip Select: When /S is high,any command means
No Operation.
Input
Input
Input
Combination of /RAS,/CAS,/W defines basic
commands.
A0-12 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-12.The Column
Address is specified by A0-9,11.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is specifies the four bank to which
a command is applied.BA must be set with ACT ,PRE
,READ ,WRITE commands
Data In and Data out are referenced to the rising edge
Input/Output of CK
Din Mask/Output Disable:When DQMB is high in burst
Input
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Power Supply for the memory mounted
Power Supply
module.
Register enable:When REGE is low,All control signals and
Input
address are buffered. (Buffer mode) When REGE is
high,All control and address are latched. (Latch mode)
MIT-DS-0385-0.1
MITSUBISHI
ELECTRIC
27.Feb.2001 4
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