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IDT72V71623

3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 2,048 x 2,048

Integrated Device Technology 

IDT72V71623 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 2,048 x 2,048

COMMERCIAL TEMPERATURE RANGE

evaluation starts. Two frames later, the complete frame evaluation (CFE) bit of

the frame alignment register (FAR) changes from low to high to signal that a valid

offset measurement is ready to be read from bits 0 to 11 of the FAR register. The

SFE bit must be set to zero before a new measurement cycle is started.

In ST-BUS ® mode, the falling edge of the frame measurement signal (FE)

is evaluated against the falling edge of the ST-BUS ® frame pulse. In GCI mode,

the rising edge of FE is evaluated against the rising edge of the GCI frame pulse.

See Table 6 and Figure 5 for the description of the frame alignment register.

delay equates to 12 output channel time slots. See Figure 2 for this example and

other examples of minimum delay to guarantee transmission in the same frame.

CONSTANT DELAY MODE (MOD1-0 = 0x1)

In this mode, frame integrity is maintained in all switching configurations by

making use of a multiple Data Memory buffer. Input channel data is written into

the Data Memory buffers during frame n will be read out during frame n+2.

Figure 1 shows examples of Constant Delay mode.

MEMORY BLOCK PROGRAMMING

The IDT72V71623 provides users with the capability of initializing the entire

Connection Memory block in two frames. To set bits 15 to 13 of every Connection

Memory location, first program the desired pattern in bits 9 to 7 of the Control

Register.

Setting the memory block program (MBP) bit of the control register high

enables the block programming mode. When the block programming enable

(BPE) bit of the Control Register is set to high, the block programming data will

be loaded into the bits 15 to 13 of every Connection Memory location. The other

Connection Memory bits (bit 12 to bit 0) are loaded with zeros. When the memory

block programming is complete, the device resets the BPE bit to zero.

LOOPBACK CONTROL

The loopback control (LPBK) bit of each Connection Memory location allows

the TX output data to be looped backed internally to the RX input for diagnostic

purposes.

If the LPBK bit is high, the associated TX output channel data is internally

looped back to the RX input channel (i.e., data from TXn channel m routes to

the RXn channel m internally); if the LPBK bit is low, the loopback feature is

disabled. For proper per-channel loopback operation, the contents of frame

delay offset registers must be set to zero and the device must be in regular switch

mode (DR3-0 = 0x0, 0x1 or 0x2).

MICROPROCESSOR INTERFACE

The IDT72V71623’s microprocessor interface looks like a standard RAM

interface to improve integration into a system. With a 14-bit address bus and a

16-bit data bus, read and writes are mapped directly into Data and Connection

memories and require only one Master Clock cycle to access. By allowing the

internal memories to be randomly accessed in one cycle, the controlling

microprocessor has more time to manage other peripheral devices and can

more easily and quickly gather information and setup the switch paths.

Table 2 shows the mapping of the addresses into internal memory blocks,

Table 3 shows the Control Register information and Figure 11 and Figure 12

shows asynchronous and synchronous microprocessor accesses.

MEMORY MAPPING

The address bus on the microprocessor interface selects the internal

registers and memories of the IDT72V71623. The two most significant bits of the

address select between the registers, Data Memory, and Connection Memory.

If A13 and A12 are HIGH, A11-A0 are used to address the Data Memory (Read

Only). If A13 is HIGH and A12 is LOW, A11-A0 are used to address Connection

Memory (Read/Write). If A13 is LOW and A12 is HIGH A11-A9 are used to select

the Control Register, Frame Alignment Register, and Frame Offset Registers.

See Table 2 for mappings.

DELAY THROUGH THE IDT72V71623

The switching of information from the input serial streams to the output serial

streams results in a throughput delay. The device can be programmed to

perform time-slot interchange functions with different throughput delay capabili-

ties on a per-channel basis. For voice applications, Variable throughput delay

is best as it ensures minimum delay between input and output data. In wideband

data applications, Constant throughput delay is best as the frame integrity of the

information is maintained through the switch.

The delay through the device varies according to the type of throughput

delay selected in the MOD1 and MOD0 bits of the Connection Memory.

CONTROL REGISTER

As explained in the Serial Data Interface Timing and Switching Configura-

tions sections, after system power-up, the Control Register should be pro-

grammed immediately to establish the desired switching configuration.

The data in the Control Register consists of the Memory Block Programming

bit (MBP), the Block Programming Data (BPD) bits, the Begin Block Program-

ming Enable (BPE), the Output Stand By (OSB), Start Frame Evaluation (SFE),

and Data Rate Select bits (DR 3-0). As explained in the Memory Block

Programming section, the BPE begins the programming if the MBP bit is enabled.

This allows the entire Connection Memory block to be programmed with the

Block Programming Data bits.

VARIABLE DELAY MODE (MOD1-0 = 0x0)

In this mode, the delay is dependent only on the combination of source and

destination serial stream speed. Although the minimum delay achievable is

dependent on the input and output serial stream speed, if data is switched

out +3 channels of the slowest data rate, the data will be switched out in the same

frame except if the input and output data rates are both 16 Mb/s (DR3-0 = 0x3).

(See Figure 2 for example).

For example, given the input data rate is 2 Mb/s and the output data rate is

8 Mb/s, input channel CH0 can be switch out by output channel CH12. In the

above example the input streams are slower than the output streams. Also, for

every 2 Mb/s time slot there are four 8 Mb/s time slots, thus a three 2 Mb/s channel

CONNECTION MEMORY CONTROL

If the ODE pin or the OSB bit is high, the MOD1-0 bits of each Connection

Memory location controls the output drivers. See Table 1 for detail. The

Processor Channel (PC) mode is entered by a 1-0 of the MOD1-0 of the

Connection Memory. In Processor Channel Mode, this allows the microproces-

sor to access TX output channels. Once the MOD1-0 bits are set the lower 8

bits of the Connection Memory will be output on the TX serial streams. Also

controlled in the Connection Memory is the Variable Delay mode or Constant

Delay mode. Each Connection Memory location allows the per-channel

selection between Variable and Constant throughput Delay modes and

Processor mode.

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