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IDT72V71623

3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 2,048 x 2,048

Integrated Device Technology 

IDT72V71623 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 2,048 x 2,048

COMMERCIAL TEMPERATURE RANGE

DESCRIPTION (CONTINUED

Output enable indications are provided through dedicated pins (one pin per

output stream) to facilitate external data bus control.

The IDT72V71623 is capable of switching up to 2,048 x 2,048 channels

without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the

device maintains frame integrity in data applications and minimizes throughput

delay for voice applications on a per channel basis.

The serial input streams (RX) and serial output streams (TX) of the

IDT72V71623 can be run up to 16.384 Mb/s allowing 256 channels per 125µs

frame. Depending on the input and output data rates the device can support

up to 16 serial streams.

With two main operating modes, Processor mode and Connection Mode,

the IDT72V71623 can easily switch data from incoming serial streams (Data

Memory) or from the controlling microprocessor (Connection Memory). As

control and status information is critical in data transmission, the Processor mode

is especially useful when there are multiple devices sharing the input and output

streams.

With two main configuration modes, Regular and Mux/Demux mode the

IDT72V71623 is designed to work in a mixed data-rate environment. In Mux/

Demux mode, all of the input streams work at one data rate and the output streams

at another. Depending on the configuration, more or less serial streams will be

available on the inputs or outputs to maintain a non-blocking switch.

With data coming from multiple sources and through different paths, data

entering the device is often delayed. To handle this problem, the IDT72V71623

has a frame evaluation feature to allow individual streams to be offset from the

frame pulse in half clock-cycle intervals up to +4.5 clock cycles for speeds up

to 8 Mb/s or +2.5 clock cycles for 16 Mb/s. (See Table 8 for maximum allowable

skew).

The IDT72V71623 also provides a JTAG test access port, an internal

loopback feature, memory block programming, a simple microprocessor

interface and automatic ST-BUS®/GCI sensing to shorten setup time, aid in

debugging and ease use of the device without sacrificing capabilities.

FUNCTIONAL DESCRIPTION

DATA AND CONNECTION MEMORY

All data that comes in through the RX inputs go through a serial-to-parallel

conversion before being stored into internal Data Memory. The 8 KHz frame

pulse (F0i) is used to mark the 125µs frame boundaries and to sequentially

address the input channels in Data Memory. The Data Memory is only written

by the device from the RX streams and can be read from either the TX streams

or the microprocessor.

Data output on the TX streams may come from either the Serial Input Streams

(Data Memory) or from the microprocessor (Connection Memory). In the case

that RX input data is to be output, the addresses in Connection Memory are used

to specify a stream and channel of the input. The Connection Memory is setup

in such a way that each location corresponds to an output channel for each

particular stream. In that way, more than one channel can output the same data.

In Processor mode, the microprocessor writes data to the Connection Memory

locations corresponding to the stream and channel that is to be output. The lower

byte (8 least significant bits) of the Connection Memory is output every frame

until the microprocessor changes the data or mode of the channel. By using this

Processor mode capability, the microprocessor can access input and output

time-slots on a per channel basis.

The most significant bits of the Connection Memory are used to control per

channel functions such as Processor mode, Constant or Variable Delay mode,

three-state of output drivers, and the Loopback function.

OPERATING MODES

In addition to Regular mode where input and output streams are operating

at the same rate, the IDT72V71623 incorporates a rate matching function,

Mux/Demux mode. In Mux/Demux mode, all input streams are operating at

the same rate, while output streams are operating at a different rate. All

configurations are non-blocking. These modes can be entered by setting the

DR3-0 bits in the Control Register, see Table 5.

OUTPUT IMPEDANCE CONTROL

In order to put all streams in three-state, all per-channel three-state control

bits in the Connection Memory are set (MOD0 and MOD1 = 1) or both the ODE

pin and the OSB bit of the Control Register must be zero. If any combination

other than 0-0, for the ODE pin and the OSB bit, is used, the three-state control

of the streams will be left to the state of the MOD1 and MOD0 bits of the Connection

Memory. The IDT72V71623 incorporates a memory block programming

feature to facilitate three-state control after reset. See Table 1 for Output High-

Impedance Control.

SERIAL DATA INTERFACE TIMING

When a 16Mb/s serial data rate is required, the master clock frequency

will be running at 16.384MHz resulting in a single-bit per clock. For all other

cases, 2Mb/s, 4Mb/s, and 8Mb/s, the master clock frequency will be twice the

fastest data rate on the serial streams. Use Table 5 to determine clock speed

and DR3-0 bits in the Control Register to setup the device. The IDT72V71623

provides two different interface timing modes, ST-BUS® or GCI. The

IDT72V71623 automatically detects the presence of an input frame pulse and

identifies it as either ST-BUS® or GCI.

In ST-BUS®, when running at 16.384MHz, data is clocked out on the

falling edge and is clocked in on the subsquent rising-edge. At all other data

rates, there are two clock cycles per bit and every second falling edge of the

master clock marks a bit boundary and the data is clocked in on the rising edge

of CLK, three quarters of the way into the bit cell. See Figure 15 for timing.

In GCI format, when running at 16.384MHz, data is clocked out on the

rising edge and is clocked in on the subsquent falling edge. At all other data

rates, there are two clock cycles per bit and every second rising edge of the

master clock marks the bit boundary and data is clocked in on the falling edge

of CLK at three quarters of the way into the bit cell. See Figure 16 for timing.

INPUT FRAME OFFSET SELECTION

Input frame offset selection allows the channel alignment of individual input

streams to be offset with respect to the output stream channel alignment (i.e. F0i).

Although input data is synchronous, delays can be caused by variable path

serial backplanes and variable path lengths, which may be implemented in large

centralized and distributed switching systems. Because data is often delayed

this feature is useful in compensating for the skew between clocks.

Each input stream can have its own delay offset value by programming the

frame input offset registers (FOR, Table 7). The frame offset shown is a function

of the data rate, and can be as large as +4.5 master clock (CLK) periods forward

with a resolution of ½ clock period. To determine the maximum offset allowed

see Table 8.

SERIAL INPUT FRAME ALIGNMENT EVALUATION

The IDT72V71623 provides the frame evaluation (FE) input to determine

different data input delays with respect to the frame pulse F0i. Setting the start

frame evaluation (SFE) bit low for at least one frame starts a measurement cycle.

When the SFE bit in the Control Register is changed from low to high, the

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