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IDT72V71623

3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 2,048 x 2,048

Integrated Device Technology 

IDT72V71623 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 2,048 x 2,048

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION

SYMBOL

NAME

I/O

DESCRIPTION

GND Ground.

Ground Rail.

Vcc

Vcc

+3.3 Volt Power Supply.

TX0-15 TX Output 0 to 15

(Three-state Outputs)

O Serial data output stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s,

or 16.384 Mb/s.

OEI0-15 Output Enable

Indication 0 to 15

(Three-state Outputs)

O These pins reflect the active or three-state status for the corresponding, (TX0-15) output streams.

RX0-15 RX Input 0 to 15

I Serial data input stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s,

or 16.384 Mb/s.

F0i

Frame Pulse

I This input accepts and automatically identifies frame synchronization signals formatted according to

ST-BUS® and GCI specifications.

FE/HCLK Frame Evaluation/

HCLK Clock

I When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK

(4.096 MHZ clock) is required for frame alignment in the wide frame pulse (WFP) mode.

CLK

Clock

I Serial clock for shifting data in/out on the serial streams (RX/TX 0-15).

TMS

Test Mode Select

I JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal

pull-up when not driven.

TDI

Test Serial Data In

I JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up

when not driven.

TDO

Test Serial Data Out

O JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when

JTAG scan is not enabled.

TCK

TRST

Test Clock

Test Reset

RESET Device Reset

I Provides the clock to the JTAG test logic.

I Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled

by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure

that the IDT72V71623 is in the normal functional mode.

I This input (active LOW) puts the IDT72V71623 in its reset state that clears the device internal counters, registers

and brings TX0-15 and microport data outputs to a high-impedance state. In normal operation, the RESET

pin must be held LOW for a minimum of 100ns to reset the device.

WFPS

Wide Frame Pulse Select I When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in

ST-BUS® /GCI mode.

DS

Data Strobe

R/W

Read/Write

CS

Chip Select

I This active LOW input works in conjunction with CS to enable the read and write operations.

I This input controls the direction of the data bus lines during a microprocessor access.

I Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V71623.

A0-13 Address Bus 0 to 13

I These pins allow direct access to Connection Memory, Data Memory and internal control registers.

D0-15

DTA

Data Bus 0-15

Data Transfer

Acknowledgment

I/O These pins are the data bits of the microprocessor port.

O This active LOW signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives

HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up

resistor is required to hold a HIGH level when the pin is in high-impedance.

ODE

Output Drive Enable

I This is the output enable control for the TX0-15 serial outputs. When ODE input is LOW and the OSB bit of

the IMS register is LOW, TX0-15 are in a high-impedance state. If this input is HIGH, the TX0-15 output

drivers are enabled. However, each channel may still be put into a high-impedance state by using the per

channel control bit in the Connection Memory.

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