IDT71V35761SA200BQ Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT71V35761SA200BQ
Integrated Device Technology
IDT71V35761SA200BQ Datasheet PDF : 22 Pages
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IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1, 2)
Operation
GW
BWE
BW1
BW2
BW3
BW4
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write all Bytes
L
X
X
X
X
X
Write all Bytes
H
L
L
L
L
L
Write Byte 1(3)
H
L
L
H
H
H
Write Byte 2(3)
H
L
H
L
H
H
Write Byte 3(3)
H
L
H
H
L
H
Write Byte 4(3)
H
L
H
H
H
L
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V35781.
3. Multiple bytes may be selected during the same cycle.
5301 tbl 12
Asynchronous Truth Table(1)
Operation(2)
OE
ZZ
I/O Status
Power
Read
L
L
Data Out
Active
Read
H
L
High-Z
Active
Write
X
L
High-Z – Data In
Active
Deselected
X
L
High-Z
Standby
Sleep Mode
X
H
High-Z
Sleep
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
5301 tbl 13
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
1
0
0
1
0
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
5301 tbl 14
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
A1
A0
A1
A0
First Address
0
0
0
1
Second Address
0
1
1
0
Third Address
1
0
1
1
Fourth Address(1)
1
1
0
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.1412
Sequence 3
A1
A0
1
0
1
1
0
0
0
1
Sequence 4
A1
A0
1
1
0
0
0
1
1
0
5301 tbl 15
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