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IDT5V9882T

3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

Integrated Device Technology 

IDT5V9882T

3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

I2C BUS DC CHARACTERISTICS

Symbol Parameter

Conditions

VIH

Input HIGH Level

VIL

Input LOW Level

VHYS

Hysteresis of Inputs

IIN

Input Leakage Current

VOL

Output LOW Voltage

IOL = 3 mA

INDUSTRIAL TEMPERATURE RANGE

Min

Typ

Max

Unit

0.7 * VDD

V

0.3 * VDD

V

0.05 * VDD

V

±1.0

μA

0.4

V

I2C BUS AC CHARACTERISTICS FOR STANDARD MODE

Symbol Parameter

Min

Typ

Max

Unit

FSCLK

Serial Clock Frequency (SCLK)

0

100

KHz

tBUF

Bus free time between STOP and START

4.7

μs

tSU:START

tHD:START

Setup Time, START

Hold Time, START

4.7

μs

4

μs

tSU:DATA

Setup Time, data input (SDAT)

250

ns

tHD:DATA

Hold Time, data input (SDAT)(1)

0

μs

tOVD

Output data valid from clock

CB

Capacitive Load for Each Bus Line

tR

Rise Time, data and clock (SDAT, SCLK)

3.45

μs

400

pF

1000

ns

tF

Fall Time, data and clock (SDAT, SCLK)

300

ns

tHIGH

HIGH Time, clock (SCLK)

tLOW

LOW Time, clock (SCLK)

4

μs

4.7

μs

tSU:STOP

Setup Time, STOP

4

μs

NOTE:

1. A device must internally provide a hold time of at least 300ns for the SDAT signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge

of SCLK.

I2C BUS AC CHARACTERISTICS FOR FAST MODE

Symbol Parameter

Min

Typ

Max

Unit

FSCLK

Serial Clock Frequency (SCLK)

0

400

KHz

tBUF

Bus free time between STOP and START

1.3

μs

tSU:START Setup Time, START

0.6

μs

tHD:START Hold Time, START

0.6

μs

tSU:DATA

Setup Time, data input (SDAT)

100

ns

tHD:DATA

Hold Time, data input (SDAT)(1)

0

μs

tOVD

Output data valid from clock

CB

Capacitive Load for Each Bus Line

0.9

μs

400

pF

tR

Rise Time, data and clock (SDAT, SCLK)

20 + 0.1 * CB

300

ns

tF

Fall Time, data and clock (SDAT, SCLK)

20 + 0.1 * CB

300

ns

tHIGH

HIGH Time, clock (SCLK)

0.6

μs

tLOW

LOW Time, clock (SCLK)

1.3

μs

tSU:STOP

Setup Time, STOP

0.6

μs

NOTE:

1. A device must internally provide a hold time of at least 300ns for the SDAT signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge

of SCLK.

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