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IDT5V9882T

3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

Integrated Device Technology 

IDT5V9882T

3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

INDUSTRIAL TEMPERATURE RANGE

POWER UP AND POWER SAVING FEATURES

If a global shutdown is enabled, SHUTDOWN/SUSPEND/OE pin asserted, most of the chip except for the PLLs will be powered down. In order to have a

complete power down of the chip, the PLLs must be powered down via the SUSPEND function or by setting the pre-scaler bits to '0x00' and disable the internal

GINx signals via the enable bits at memory address 0x05. Note that the register bits will not lose their state in the event of a chip power-down. The only possibility

that the register bits will lose their state is if the part was power-cycled. After coming out of shutdown mode, the PLLs will require time to relock.

During power up, the values of GIN1 and GIN0 will be latched and used for PLL configuration selection, regardless of the state of the I2C_MFC pin and GINx

being disabled via the GINENx bits. The GIN pins should be held LOW during power up to select configuration0 as default. The output levels will be at an undefined

state during power up.

The post-divider should never be disabled via PM bits after power up, or else it will render the output bank completely non-functional during normal operation,

(unless the output bank itself will not be used at all).

During power up, the VDD ramp must be monotonic.

CLOCK SWITCH MATRIX AND OUTPUTS

All three PLL outputs and the currently selected input clock source are routed into and through a clock matrix. The user is able to select which PLL output and

clock source is routed to which output bank via the SRCx bits (0x34, 0x35). Each output bank has its own set of SRC bits. Refer to the RAM table for more

information. Note that OUT1 will be based off the reference clock and the only output bank toggling under the default RAM bit settings.

Outputs 1, 2 and 4 are 3.3V LVTTL. Outputs bank 3 can be 3.3V LVTTL, LVPECL or LVDS. The LVDS and LVPECL selection is determined by the LVLx

bits (0x54, 0x58). Each output bank has individual slew-rate control (SLEWx bits). Each output can be individually inverted (INVx bits); when using LVPECL

or LVDS modes, one of the outputs in each LVPECL/LVDS pair should be inverted. All output banks except OUT1 have a programmable 10-bit post-divider

(Qx bits) with two selectable divide configurations via the ODIVx bits.

There are four settings for the programmable slew rate, 0.7V/ns, 1.25V/ns, 2V/ns, and 2.75V/ns; this only applies to the 3.3V LVTTL outputs. The differential

outputs are not slew rate programmable in LVPECL or LVDS modes. SLEW3 must be set to 2.75V/ns for stable output operation . For LVTTL output frequency

rates higher than 100MHz, a slew rate of 2V/ns or greater should be selected. Each output can also be enabled/disabled, which is described in the 'SHUTDOWN/

SUSPEND/ENABLE of OUTPUTS' section. Refer to the RAM table for all binary settings.

HIGH LEVEL BLOCK DIAGRAM FOR CONFIGURATION SCHEME

I/Os

I/Os

PLLs and Control

Blocks

Non-Volatile

Configuration

EEPROM

Cell

I 2C interface

Volatile

Configuration

Programming

Interface Block

NOTE: Diagram does not represent actual number of die on chip.

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