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IDT5V9882T

3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

Integrated Device Technology 

IDT5V9882T

3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

INDUSTRIAL TEMPERATURE RANGE

Understanding the GIN Signals

During power up, the part will virtually be in MFC mode2, therefore, the values of GIN1 and GIN0 will be latched and used for PLL configuration selection,

regardless of the state of the I2C_MFC pin. This means that when in programming mode, the PLL configuration can only be changed by writing directly to the

registers of the currently selected configuration. When in MFC mode, configuration 0 or 1 should be selected if you do not want to change configurations when

entering or leaving programming mode. The GIN pins should be held LOW during power up to select configuration0 as default.

When not in programming mode, the GIN inputs directly control the selected configuration. The internal GINx signals can be individually disabled via

programming the GINEN bits (0x06). When disabled by setting GINENx to "0", the GINx inputs may be left floating, but during power up, the GIN pins will still

latch. Disabled inputs are interpreted as LOW by the internal state machines. Even if disabled, GIN1 and GIN0 pins will be enabled if required for I2C_MFC

programming functions when in programming mode.

SHUTDOWN/SUSPEND/ENABLE OF OUTPUTS

There are two external pins along with internal bits that control the enabling/disabling of the output banks. The SHUTDOWN/SUSPEND/OE pin, along with

the internal bits, control the enabling and disabling of the output bank and PLLs. This pin can be programmed to function as an output enable, PLL power down,

or global shutdown. The polarity of the SHUTDOWN/OE signal pin can be programmed to be either active HIGH or LOW with the SP bit (0x1C). When SP

is "0", the pin becomes active HIGH and when SP is "1", the pin becomes active LOW. The SH bit(0x1C) determines the function of the SHUTDOWN/OE

signal pin. If SH is "1", the signal pin is SHUTDOWN and functions as a global shutdown. This will override the OEx (0x1C), OSx (0x1D), and PLLSx (0x1E)

bits. If SH is "0", the signal pin is OE and functions as an enable/disable of the output banks. If used as an output enable/disable, each output bank can be individually

programmed to be enabled or disabled by the OE pin.by setting OEx bits to "1". If the OE signal pin is asserted, the output banks that has their corresponding

OEx bit set to "1" will be disabled. The OEMx bits determine the outputs' disable state. When set to "0x" the outputs will be tristated. When set to "10", the outputs

will be pulled low. When set to "11", the outputs will be pulled high. Inverted outputs will be parked in the opposite state. If the OEx bits are set to "0", the states

of the corresponding output banks will not be impacted by the state of the OE pin. To individually enable/disable via programming instead of the OE pin, hard

wire the OE pin to Vdd or GND (depending if it is active HIGH or LOW) as if to disable the outputs. Then toggle the OEx bits to either "0" to enable or "1" to

disable.

When the chip is in shutdown, the outputs, the reference oscillator, and the I2C_MFC pin are powered down. The outputs will be tristated and the I2C_MFC

pin will be set to MFC mode (MID level). Programming will not be allowed. The GINx pins and clock inputs remain operational. The PLL is not disabled. The

SHUTDOWN pin must be deasserted in order to program the part or to resume operation.

The SUSPEND function can be used to power down the PLL and/or output banks. Each output bank can be individually programmed to be enabled or

disabled by the SUSPEND signal pin by setting the OSx bits to "1". If the SUSPEND signal pin is asserted, the output banks that has their corresponding OSx

bit set to "1" will be powered down and outputs tristated. If the OSx bits are set to "0", the states of the corresponding output banks will not be impacted by the

state of the SUSPEND pin. There is also an option to suspend individual PLLs by setting the PLLSx bits (0x1E) to "1". This will associate the PLL to the SUSPEND

pin. When the pin is asserted, the corresponding PLLs will be powered down. It will not only power down the PLL but also any output bank associated with

it. The PLLSx bits will override the OSx bits.

In the event of a PLL suspend, the PLL must achieve lock again after it has been re-enabled, In the event of a global shutdown, the PLL does not have

to re-acquire lock since it is not disabled.

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