IDT5V2305(2010) Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT5V2305
(Rev.:2010)

2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER

Integrated Device Technology 

IDT5V2305

2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER

INDUSTRIAL TEMPERATURE RANGE

OUTPUT ENABLE GLITCH SUPPRESSION CIRCUIT

The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the clock input such that the output buffer will be

enabled on the next full period of the input clock (negative edge triggered by the input clock). The G input must be stable one tEN - time prior to the falling edge

of the CLK for predictable operation.

CLK

Gx

tEN

Yx

tDIS

G (tEN, tDIS) Relative to CLK↓

6

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