IDT49C465PQF Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT49C465PQF Datasheet PDF : 38 Pages
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IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
AC TIMING DIAGRAMS — 64-BIT CONFIGURATION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SINGLE
465
to
1
2
3
4
5
Parameter
Name
Propagation Delay
From
To
Min./
Max.
SOE
(SOE = Tied high)
SD Bus
SLE
MOE
Valid DATAIN
t SSLS
t SSLH
(1)
t SLC
(MOE = Tied high)
t SSLS
t SSLH
SDIN Set-up to SLEIN = Low
SDIN Hold to SLEIN = Low
t SLC(1) SLE = High to CBO(1)
min.
min.
max.
MD Bus
MLE
CBOE
CBO
Valid DATAIN
t MMLS
t MMLH
t MMLS MDIN Set-up to MLEIN = Low
min.
t MMLH MDIN Hold to MLEIN = Low
min.
t SC
t MC
t MLC (2)
t CECZx
t SC
Bits 32–63 to CBO
max.
t MC
t MLC(2)
Bits 0–31 to CBO
MLEIN = High to CBO (2)
max.
max.
t CECZx CBOE = Low to CBO Enabled
max.
Final Checkbits Out
to
1
2
3
4
5
NOTE:
1. Assumes that System Data is valid at least 3ns (Com.) before SLE goes HIGH.
2. Assumes that Memory Data is valid at least 4ns (Com.) before MLE goes HIGH.
Figure 14. 64-Bit Single Chip "Generate Only" Timing
2552 drw 26
11.7
35
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