IDT49C465APQF Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT49C465APQF Datasheet PDF : 38 Pages
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IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TIMING DIAGRAMS — 64-BIT CONFIGURATION
BOTH
465s
to
1
2
3
4
5
Parameter
Name
Propagation Delay
From
To
Min./
Max.
BEN
SOE
t SESxZ
t SESxZ
SD (L & U) (OUTPUT)
DATAIN
t SSLS
t SSLH
SLE
t SESxZ min. SOE = High to SDOUT Disabled min.
t SESxZ max. SOE = High to SDOUT Disabled max.
t SSLS
SDIN Set-up to SLEIN = Low
min.
t SSLH
SDIN Hold to SLEIN = Low
min.
Px
Parity In
t PPE
t PPE
Px to PERR
max.
PERR
MOE
t SLM (1)
t MEMZx
t BEM
MD (L & U) (INPUT)
CBOE
CBO
t CECZx
LOWER 465
UPPER 465
PCBI
t SM
t SM
SDIN to MDOUT
MD DATAOUT = SD DATAIN
t SC
t SLC (1)
t SLM (1)
t MEMZx
t BEM
t SC
t SLC (1)
SLE = High to MDOUT
MOE = Low to MDOUT Enabled
BEN to MDOUT
SD Lower In to CBO
SLEIN = High to CBO (1)
t CECZx
CBOE = Low to CBO Enabled
Partial Checkbits Out
3
Inter-chip delay (Design dependent)
Partial Checkbits In
t PCC
t PCC
PCBI to CBO
max.
max.
max.
max.
max.
max.
max.
max.
CBO
Final Checkbits Out
to
1
2
3
4
5
NOTE:
1. Assumes that System Data is valid at least 3ns (Com.)/4ns (Mil.) before SLE goes HIGH.
Figure 10. 64-Bit Generate Timing — (64-Bit Cascading System)
2552 drw 22
11.7
31
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