IDT49C465GB Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT49C465GB Datasheet PDF : 38 Pages
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IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
AC TIMING DIAGRAMS — 32-BIT CONFIGURATION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
to
1
2
3
4
5
Parameter
Name
Propagation Delay
From
To
Min./
Max.
MOE
MD 0–31
t MEMxZ
(OUTPUT)
Valid DATAIN
t MMLS
t MMLH
CBI
Valid Checkbits In
t CMLS
t CMLH
MLE
PLE
BEN
SOE
P0–3
t MLS(1)
t PLS (1)
t BESZx
t SESZx
t CS
t MS
t MP
t MLP
t PLP
t BEPZx
t SEP
Corrected DATAOUT
Parity Out
t MEMxZ MOE = High to MDOUT Disabled
max.
t MMLS MDIN Set-up to MLE = Low
min.
t MMLH MDIN Hold to MLE = Low
min.
t CMLS Checkbit Set-up to MLE = Low
min.
t CMLH Checkbit Hold to MLE = Low
min.
t MLS(1)
(1)
MLEIN = High to SDOUT
max.
t PLS(1) PLE = Low to SDOUT (1)
max.
t BESZx BEN = High to SDOUT Enabled
max.
t SESZx SOE = Low to SDOUT Enabled
max.
t CS
CBI to Corrected SDOUT
max.
t MS
MDIN to Corrected SDOUT
max.
t MP
MDIN to Parity Out
max.
t MLP
MLE = High to Parity Out
max.
t PLP
PLE = Low to Parity Out
max.
t BEPZx BEN = High to Parity Out
max.
t SEP
SOE = Low to Parity Out
max.
to
1
2
3
4
5
NOTE:
1. Assumes that Memory Data and Checkbits are valid at least 3ns (Com.)/4ns (Mil.) before MLE goes HIGH.
Figure 9. 32-Bit Correct Timing
2552 drw 21
11.7
30
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