IDT49C465AG Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT49C465AG Datasheet PDF : 38 Pages
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IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
AC TIMING DIAGRAMS — 32-BIT CONFIGURATION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
to
1
2
3
4
5
Parameter
Name
Propagation Delay
From
To
Min./
Max.
MOE
t MEMxZ
MD 0–31 (OUTPUT)
Valid DATAIN
t MMLS
t MMLH
CBI
Valid Checkbits In
t CMLS
t CMLH
MLE
SYO
ERR
MERR
t MSY
t CSY
t MLSY (1)
t ME
t CE
t MLEx (1)
t MME
t CME
t MLMEx (1)
t MEMxZ MOE = High to MDOUT Disabled
max.
t MMLS MDIN Set-up to MLE = Low
min.
t MMLH MDIN Hold to MLE = Low
min.
t CMLS Checkbit Set-up to MLE = Low
min.
t CMLH Checkbit Hold to MLE = Low
min.
t MSY
t CSY
t MLSY(1)
MDIN to SYOOUT
Checkbits in to SYOOUT
MLE = High to SYOOUT
max.
max.
max.
t ME
MDIN to ERR = Low
max.
t CE
Checkbits in to ERR = Low
max.
t MLEx(1) MLE = High to ERR = Low(1)
max.
t MME
t CME
t MLEMx(1)
MDIN to MERR = Low
Checkbits in to MERR = Low
MLE = High to MERR = Low (1)
max.
max.
max.
to
1
2
3
4
5
NOTE:
1. Assumes that Memory Data and Checkbits are valid at least 3ns (Com.)/4ns (Mil,) before MLE goes HIGH.
Figure 8. 32-Bit Detect Timing
2552 drw 20
11.7
29
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