IDT49C465PQFB Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT49C465PQFB Datasheet PDF : 38 Pages
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IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
AC TIMING DIAGRAMS — 32-BIT CONFIGURATION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
to
1
2
3
4
5
Parameter
Name
Propagation Delay
From
To
Min./
Max.
BEN
t BESxZ
t BESxZ
SOE
t SESxZ
t SESxZ
SD0–31 (OUTPUT)
DATAIN
t SSLS
t SSLH
SLE
t BESxZ min. BEN = Low to SDOUT Disabled min.
t BESxZ max. BEN = Low to SDOUT Disabled max.
t SESxZ min. SOE = Low to SDOUT Disabled
min.
t SESxZ max. SOE = Low to SDOUT Disabled
max.
t SSLS
SDIN Set-up to SLEIN = Low
min.
t SSLH
SDIN Hold to SLEIN = Low
min.
t SPE
t SPE
SDIN to PERROUT
max.
PN
t PPE
t PPE
Px to PERROUT
max.
PERR
t SM
t SLM (1)
MOE
MD0–31
tMEMZx
(INPUT)
M DATAOUT = S DATAIN
t SC
t SLC (1)
CBOE
t CECZx
CBO
t SM
t SLM (1)
SDIN to MDOUT
SLE = High to MDOUT
max.
max.
t MEMZx
MOE = Low to MDOUT Enabled max.
t SC
t SLC(1)
SDIN to CBO
SLE = High to CBO
max.
max.
t CECZx CBOE = Low to CBO Enable max.
to
1
2
3
4
5
NOTE:
1. Assumes that System Data is valid at least 3ns (Com.) before SLE goes HIGH.
Figure 7. 32-Bit Generate Timing
2552 drw 19
11.7
28
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