HT49C30-1 Ver la hoja de datos (PDF) - Holtek Semiconductor
Número de pieza
componentes Descripción
Fabricante
HT49C30-1 Datasheet PDF : 43 Pages
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HT49R30A-1/HT49C30-1/HT49C30L
The PFD output signal function is controlled by the PA3 data register and the timer/event counter state. The PFD output
signal frequency is also dependent on the timer/event counter overflow period. The definitions of PFD control signal
and PFD output frequency are listed in the following table.
Timer Timer Preload Value
PA3 Data Register
PA3 Pad State
PFD Frequency
OFF
X
0
U
X
OFF
X
1
0
X
ON
N
ON
N
0
PFD
fINT/[2´(256-N)]
1
0
X
Note: ²X² stands for unused
²U² stands for unknown
D a ta B u s
W r ite
C h ip R e s e t
D
Q
CK Q
S
V DD
V DD
W eak
P u ll- u p
C /N M O S
O p tio n
(P A 0 ~ P A 3 )
O p tio n
(P A 0 ~ P A 3 )
P A 0~P A 7
D a ta b u s
R e a d I/O
V DD
W eak
P u ll- u p
P B 0~P B 5
R e a d I/O
S y s te m
W a k e -u p
( P A o n ly )
O p tio n
PA Input/output ports
LCD display memory
The device provides an area of embedded data memory
for LCD display. This area is located from 40H to 52H of
the RAM at Bank 1. Bank pointer (BP; located at 04H of
the RAM) is the switch between the RAM and the LCD
display memory. When the BP is set as ²01H², any data
written into 40H~52H will effect the LCD display. When
the BP is cleared to ²00H², any data written into
40H~52H means to access the general purpose data
PB Input ports
memory. The LCD display memory can be read and
written to only by indirect addressing mode using MP1.
When data is written into the display data area, it is auto-
matically read by the LCD driver which then generates
the corresponding LCD driving signals. To turn the dis-
play on or off, a ²1² or a ²0² is written to the correspond-
ing bit of the display memory, respectively. The figure
illustrates the mapping between the display memory
and LCD pattern for the device.
COM
40H 41H 42H 43H
50
51
52
B it
0
0
1
1
2
2
3
3
SEG M ENT
Rev. 1.10
0
1
2
3
16
17
18
Display memory
19
September 25, 2002
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