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HT49R30A-1

8-Bit LCD Type MCU

Holtek Semiconductor 

HT49R30A-1/HT49C30-1/HT49C30L

Timer/Event Counter

One timer/event counters is implemented in the device.

It contains an 8-bit programmable count-up counter.

The timer/event counter clock source may come from

the system clock or system clock/4 or RTC time-out sig-

nal or external source. System clock source or system

clock/4 is selected by options. Using external clock input

allows the user to count external events, measure time

internals or pulse widths, or generate an accurate time

base. While using the internal clock allows the user to

generate an accurate time base.

There are two registers related to the timer/event coun-

ter, i.e., TMR ([0DH]) and TMRC ([0EH]). There are also

two physical registers which are mapped to TMR loca-

tion; writing TMR places the starting value in the

timer/event counter preload register, while reading it

yields the contents of the timer/event counter. TMRC is

a timer/event counter control register used to define

some options.

The TN0 and TN1 bits define the operation mode. The

event count mode is used to count external events,

which means that the clock source is from an external

TMR pin. The timer mode functions as a normal timer

with the clock source coming from the internal selected

clock source. Finally, the pulse width measurement

mode can be used to count the high or low level duration

of the external signal TMR, and the counting is based on

the internal selected clock source.

In the event count or timer mode, the timer/event coun-

ter starts counting at the current contents in the

timer/event counter and ends at FFH. Once an overflow

occurs, the counter is reloaded from the timer/event

counter preload register, and generates an interrupt re-

quest flag (TF; bit 6 of INTC0).

In the pulse width measurement mode with the values

of the TON and TE bits equal to one, after the TMR

has received a transient from low to high (or high to

low if the TE bit is ²0²), it will start counting until the

TMR returns to the original level and resets the TON.

The measured result remains in the timer/event counter

even if the activated transient occurs again. In other

words, only one cycle measurement can be made until

the TON is set. The cycle measurement will re-function

as long as it receives further transient pulse. In this oper-

ation mode, the timer/event counter begins counting ac-

cording not to the logic level but to the transient edges.

In the case of counter overflows, the counter is reloaded

from the timer/event counter preload register and issues

an interrupt request, as in the other two modes, i.e.,

event and timer modes.

To enable the counting operation, the Timer ON bit

(TON; bit 4 of TMRC) should be set to 1. In the pulse

width measurement mode, the TON is automatically

cleared after the measurement cycle is completed. But

in the other two modes, the TON can only be reset by in-

structions. The overflow of the Timer/Event Counter is

one of the wake-up sources and can also be applied to a

PFD (Programmable Frequency Divider) output at PA3

by options. No matter what the operation mode is, writing

a 0 to ETI disables the related interrupt service. When the

PFD function is selected, executing ²CLR [PA].3² instruc-

tion to enable PFD output and executing ²SET [PA].3² in-

struction to disable PFD output.

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register also re-

loads that data to the timer/event counter. But if the

timer/event counter is turn on, data written to the

timer/event counter is kept only in the timer/event coun-

ter preload register. The timer/event counter still contin-

ues its operation until an overflow occurs.

When the timer/event counter (reading TMR) is read,

the clock is blocked to avoid errors. As this may results

in a counting error, blocking of the clock should be taken

into account by the programmer.

S y s te m C lo c k

S y s te m C lo c k /4

O p tio n

R TC O ut

TN 2

TM R

M

U

f IN T

X

TN 1

TN 0

TE

TN 1

P u ls e W id th

M e a s u re m e n t

TN 0

M o d e C o n tro l

TO N

D a ta B u s

T im e r /E v e n t C o u n te r R e lo a d

P r e lo a d R e g is te r

T im e r /E v e n t

C o u n te r

O v e r flo w

to In te rru p t

TQ

P.D

Timer/Event Counter

P A 3 D a ta C T R L

Rev. 1.10

17

September 25, 2002

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