HT49C30-1 Ver la hoja de datos (PDF) - Holtek Semiconductor
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HT49C30-1 Datasheet PDF : 43 Pages
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HT49R30A-1/HT49C30-1/HT49C30L
RT2 RT1 RT0 RTC Clock Divided Factor
0
0
0
28*
0
0
1
29*
0
1
0
210*
0
1
1
211*
1
0
0
212
1
0
1
213
1
1
0
214
1
1
1
215
Note: ²*² not recommended for use
Power down operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following.
· The system oscillator turns off but the WDT or RTC
oscillator keeps running (if the WDT oscillator or the
real time clock is selected).
· The contents of the on-chip RAM and of the registers
remain unchanged.
· The WDT is cleared and start recounting (if the WDT
clock source is from the WDT oscillator or the real time
clock oscillator).
· All I/O ports maintain their original status.
· The PD flag is set but the TO flag is cleared.
· LCD driver is still running (if the WDT OSC or RTC
OSC is selected).
The system quits the HALT mode by an external reset,
an interrupt, an external falling edge signal on port A, or
a WDT overflow. An external reset causes device initial-
ization, and the WDT overflow performs a ²warm reset².
After examining the TO and PD flags, the reason for chip
reset can be determined. The PD flag is cleared by sys-
tem power-up or by executing the ²CLR WDT²
instruction, and is set by executing the ²HALT²
instruction. On the other hand, the TO flag is set if WDT
time-out occurs, and causes a wake-up that only resets
the PC (Program Counter) and SP, and leaves the oth-
ers at their original state.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program resumes execution of the next instruction.
On the other hand, awakening from an interrupt, two se-
quences may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
resumes execution at the next instruction. But if the in-
terrupt is enabled, and the stack is not full, the regular in-
terrupt response takes place.
When an interrupt request flag is set before entering the
²HALT² status, the system cannot be awaken using that
interrupt.
If wake-up events occur, it takes 1024 tSYS (system
clock period) to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the Wake-up results in
the next instruction execution, the execution will be per-
formed immediately after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which reset may occur.
· RES is reset during normal operation
· RES is reset during HALT
· WDT time-out is reset during normal operation
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a ²warm reset² that
resets only the PC and SP and leaves the other circuits
at their original state. Some registers remain unaffected
during any other reset conditions. Most registers are re-
set to the ²initial condition² once the reset conditions are
met. Examining the PD and TO flags, the program can
distinguish between different ²chip resets².
V DD
RES
Reset circuit
TO PD
RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES Wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT Wake-up HALT
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem awakes from the HALT state. Awaking from the
HALT state, the SST delay is added.
An extra option load time delay is added during reset
and power on.
Rev. 1.10
15
September 25, 2002
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