HT49RA0 Ver la hoja de datos (PDF) - Holtek Semiconductor

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HT49RA0

Remote Type 8-Bit MCU with LCD

Holtek Semiconductor 

HT49RA0/HT49CA0

Status Register - STATUS

The status register (0AH) is of 8 bits wide and contains,

a carry flag (C), an auxiliary carry flag (AC), a zero flag

(Z), an overflow flag (OV), a power down flag (PDF), and

a watchdog time-out flag (TO). It also records the status

information and controls the operation sequence.

Except the TO and PDF flags, bits in the status register

can be altered by instructions similar to other registers.

Data written into the status register does not alter the TO

or PDF flags. Operations related to the status register,

however, may yield different results from those in-

tended. The TO and PDF flags can only be changed by

a Watchdog Timer overflow, chip power-up, or clearing

the Watchdog Timer and executing the ²HALT² instruc-

tion. The Z, OV, AC, and C flags reflect the status of the

latest operations.

On entering the interrupt sequence or executing the

subroutine call, the status register will not be automati-

cally pushed onto the stack. If the contents of the status

is important, and if the subroutine is likely to corrupt the

status register, the programmer should take precautions

and save it properly.

Interrupts

The devices provides two external interrupts, one inter-

nal timer/event counter interrupts, an internal time base

interrupt, and an internal real time clock interrupt. The

interrupt control register 0 (INTC0;0BH) and interrupt

control register 1 (INTC1;1EH) both contain the interrupt

control bits that are used to set the enable/disable status

and interrupt request flags.

Once an interrupt subroutine is serviced, other inter-

rupts are all blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may take place during this interval,

but only the interrupt request flag will be recorded. If a

certain interrupt requires servicing within the service

routine, the EMI bit and the corresponding bit of the

INTC0 or of INTC1 may be set in order to allow interrupt

nesting. Once the stack is full, the interrupt request will

not be acknowledged, even if the related interrupt is en-

abled, until the Stack Pointer is decremented. If immedi-

ate service is desired, the stack should be prevented

from becoming full.

All these interrupts can support a wake-up function. As

an interrupt is serviced, a control transfer occurs by

pushing the contents of the program counter onto the

stack followed by a branch to a subroutine at the speci-

fied location in the ROM. Only the contents of the pro-

gram counter is pushed onto the stack. If the contents of

the register or of the status register (STATUS) is altered

by the interrupt service program which corrupts the de-

sired control sequence, the contents should be saved in

advance.

External interrupts are triggered by a high to low or low

to high or both transition of INT0 or INT1, and the related

interrupt request flag (EIF0;bit 4 of INTC0, EIF1;bit 5 of

INTC0) is set as well. After the interrupt is enabled, the

stack is not full, and the external interrupt is active, a

subroutine call to location 04H or 08H occurs. The inter-

rupt request flag (EIF0 or EIF1) and EMI bits are all

cleared to disable other interrupts.

Bit No.

0

1

2

3

4

5

6, 7

Label

C

AC

Z

OV

PDF

TO

¾

Function

C is set if the operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-

tate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is

set by executing the ²HALT² instruction.

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO

is set by a WDT time-out.

Unused bit, read as ²0²

Status (0AH) Register

Rev. 1.20

8

October 24, 2007

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