HT49RA0 Ver la hoja de datos (PDF) - Holtek Semiconductor
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HT49RA0 Datasheet PDF : 39 Pages
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HT49RA0/HT49CA0
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or an instruction clock
(system clock/4) or a real time clock oscillator (RTC os-
cillator). The timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The WDT can be
disabled by option. But if the WDT is disabled, all execu-
tions related to the WDT lead to no operation.
The WDT time-out period is as fS/216~fS/215.
If the WDT clock source chooses the internal WDT oscilla-
tor, the time-out period may vary with temperature, VDD,
and process variations. On the other hand, if the clock
source selects the instruction clock and the ²HALT² in-
struction is executed, WDT may stop counting and lose its
protecting purpose, and the logic can only be restarted by
an external logic.
When the device operates in a noisy environment, using
the on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT can stop the system clock.
The WDT overflow under normal operation initializes a
²chip reset² and sets the status bit ²TO². In the HALT
mode, the overflow initializes a ²warm reset², and only
the program counter and stack pointer are reset to zero.
To clear the contents of the WDT, there are three meth-
ods to be adopted, i.e., external reset (a low level to
RES), software instruction, and a ²HALT² instruction.
There are two types of software instructions; ²CLR
WDT² and the other set - ²CLR WDT1² and ²CLR
WDT2². Of these two types of instruction, only one type
of instruction can be active at a time depending on the
options - ²CLR WDT² times selection option. If the ²CLR
WDT² is selected (i.e., CLR WDT times equal one), any
execution of the ²CLR WDT² instruction clears the WDT.
In the case that ²CLR WDT1² and ²CLR WDT2² are
chosen (i.e., CLR WDT times equal two), these two in-
structions have to be executed to clear the WDT; other-
wise, the WDT may reset the chip due to time-out.
Time Base
The time base offers a periodic time-out period to gener-
ate a regular internal interrupt. Its time-out period
ranges from fS/212 to fS/215 selected by options. If time
base time-out occurs, the related interrupt request flag
(TBF; bit 4 of INTC1) is set. But if the interrupt is en-
abled, and the stack is not full, a subroutine call to loca-
tion 10H occurs.
fS
D iv id e r
P r e s c a le r
O p tio n
O p tio n
L C D D r iv e r ( fS /2 2 ~ fS /2 8 )
B u z z e r (fS /2 2 ~ fS /2 9 )
Time Base
T im e B a s e In te rru p t
(fS /2 12 ~ fS /2 15 )
Real Time Clock - RTC
The real time clock (RTC) is operated in the same man-
ner as the time base that is used to supply a regular inter-
nal interrupt. Its time-out period ranges from fS/28 to
fS/215 by software programming . Writing data to RT2,
RT1 and RT0 (bit2, 1, 0 of RTCC;09H) yields various
time-out periods. If the RTC time-out occurs, the related
interrupt request flag (RTF; bit 5 of INTC1) is set. But if
the interrupt is enabled, and the stack is not full, a subrou-
tine call to location 14H occurs. The real time clock
time-out signal also can be applied to be a clock source of
Timer/Event Counter for getting a longer time-out period.
RT2
0
0
0
0
1
1
1
1
RT1
0
0
1
1
0
0
1
1
RT0
0
1
0
1
0
1
0
1
RTC Clock Divided Factor
28*
29*
210*
211*
212
213
214
215
Note: ²*² not recommended to be used
fS
D iv id e r
P r e s c a le r
R T2
R T1
R T0
8 to 1
M ux.
fS /2 8 ~ fS /2 1 5
R T C In te rru p t
Real Time Clock
S y s te m C lo c k /4
R TC
O SC
32768H z
W
O
DT
SC
12kH
z
O p tio n fS
S e le c t
D iv id e r
P r e s c a le r
W D T C le a r
Watchdog Timer
CK T
CK T
R
R
T im e - o u t R e s e t
fS /2 16 ~ fS /2 15
Rev. 1.20
11
October 24, 2007
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