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HT46R92 Ver la hoja de datos (PDF) - Holtek Semiconductor

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HT46R92 Datasheet PDF : 61 Pages
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HT46R92
E x te rn a l E v e n t
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
Event Counter Mode Timing Chart
T im e r + 3
propriate Timer Control Register, is low, the
Timer/EventCounter will increment each time the asso-
ciated external timer pin receives a low to high transi-
tion. If the Active Edge Select bit is high, the
Timer/Event Counter will increment each time the exter-
nal timer pin receives a high to low transition. When it is
full and overflows, an interrupt signal is generated and
the Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the asso-
ciated Timer/Event Counter Interrupt Enable bit in the
Interrupt Control Register, is reset to zero.
As the external timer pin is shared with an I/O pin, to en-
sure that the pin is configured to operate as an event
counter input pin, two things have to happen. The first is
to ensure that the Operating Mode Select bits in the
Timer Control Register place the Timer/Event Counter in
the Event Counting Mode, the second is to ensure that
the port control register configures the pin as an input. It
should be noted that in the event counting mode, even if
the microcontroller is in the Power Down Mode, the
Timer/Event Counter will continue to record externally
changing logic events on the timer input pin. As a result
when the timer overflows it will generate a timer interrupt
and corresponding wake-up source.
Configuring the Pulse Width Measurement Mode
In this mode, the Timer/Event Counter can be utilised to
measure the width of external pulses applied to the ex-
ternal timer pins. To operate in this mode, the Operating
Mode Select bit pair in the appropriate Timer Control
Register must be set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Pulse Width
Measurement Mode
Bit7 Bit6
11
In this mode, a choice of internal clocks can be used as
the Timer/Event Counter clock. However this clock
source is further divided by a prescaler, the value of
which is determined by the Prescaler Rate Select bits,
which are bits 0~2 in the respective Timer Control Reg-
ister. After the other bits in the appropriate Timer Con-
trol Register have been setup, the enable bit, which is bit
4 of the Timer Control Register, can be set high to en-
able the Timer/Event Counter, however it will not actu-
ally start counting until an active edge is received on the
external timer pin.
If the Active Edge Select bit, which is bit 3 of the Timer
Control Register, is low, once a high to low transition has
been received on the related external timer pin, the
Timer/Event Counter will start counting until the external
timer pin returns to its original high level. At this point the
enable bit will be automatically reset to zero and the
Timer/Event Counter will stop counting. If the Active
Edge Select bit is high, the Timer/Event Counter will be-
gin counting once a low to high transition has been re-
ceived on the external timer pin and stop counting when
the external timer pin returns to its original low level. As
before, the enable bit will be automatically reset to zero
and the Timer/Event Counter will stop counting. It is im-
portant to note that in the Pulse Width Measurement
Mode, the enable bit is automatically reset to zero when
the external control signal on the external timer pin re-
turns to its original level, whereas in the other two
modes the enable bit can only be reset to zero under
program control.
The residual value in the Timer/Event Counter, which
can now be read by the program, therefore represents
the length of the pulse received on the external timer
pin. As the enable bit has now been reset, any further
transitions on the external timer pin will be ignored. Not
until the enable bit is again set high by the program can
E x te r n a l T im e r
P in In p u t
TO N
( w ith T E = 0 )
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
T im e r
+1
+2
+3
+4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Chart
Rev. 1.10
21
November 5, 2008

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