HT46R92 Ver la hoja de datos (PDF) - Holtek Semiconductor
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HT46R92 Datasheet PDF : 61 Pages
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HT46R92
LCD Driver Function
The device contains circuitry to control an external LCD.
This function is controlled using the LCDC register.
LCD Driver Operation
When the LCDEN bit in the LCDC register is set high
and PB is configured as an output, ports PB, PC, PD
and PE become CMOS outputs, but have lower
sink/source capabilities making them suitable for LCD
segment driving. Following a power-on reset, port PB
will be setup as an input port, while PC is setup as a
PMOS output port while PD and PE are setup as NMOS
output ports, making them suitable for LED driving.
S y s te m C lo c k
T1
T2
T3
T4
T1
T2
T3
T4
P o rt D a ta
W r ite to P o r t
R e a d fro m P o rt
Read/Write Timing
However at this time, as the LCDEN bit is low, the PC,
PD and PE outputs will be in an open-drain
high-impedance condition. To setup ports PB~PE as
CMOS outputs, the LCDEN bit must be set high. It is im-
portant to note that PB and PC have a lower sink ability
(IOL2) while PD and PE have a lower driving ability
(IOH3). The D.C. Characteristics provide for further infor-
mation.
1/2 Bias LCD Control
As the device may be conveniently used for driving LCD
panels, pins PC4~PC7 and other I/O ports can be used
together to implement 1/2 bias LCD timing signals.
COM0~3 can be sourced from the PC4~7 pins while the
SEGMENTS can be sourced from other I/O ports. The
internal 1/2 bias circuit is enabled via a combination of
the LCDEN and COM0EN~COM3EN bits in the LCDC
register. The RSEL bit in the LCDC register selects the
bias circuit resistor values which should be chosen ac-
cording to the actual LCD panel used and to minimise
current consumption. Note that there is only one bias
circuit which is shared by all the COM outputs.
LCDC Register
1/2 Bias
LCDEN COM3EN COM2EN COM1EN COM0EN On/Off
0
x
x
x
x
Off
1
0
0
0
0
Off
1
0
0
0
1
On
:
:
:
:
:
ON
:
:
:
:
:
1
1
1
1
1
ON
1/2 Bias Circuit Control
The following steps can be used to implement LCD
timing:
· Select the bias resistor by setting RSEL=0 or 1
· Set LCDEN=1
· Use software to generate the VDD, VSS, VDD/2 volt-
ages by changing COM pins PC4~7 to output high,
output low and input respectively.
· Generate the segment timing using other I/O ports
with outputs equal to either VSS or VDD
b7
b0
R S E L L C D E N C O M 3 E N C O M 2 E N C O M 1 E N C O M 0 E N L C D C R e g is te r
1 /2 B ia s C O M 0 o u tp u t e n a b le
1 : e n a b le
0 : d is a b le
1 /2 B ia s C O M 1 o u tp u t e n a b le
1 : e n a b le
0 : d is a b le
1 /2 B ia s C O M 2 o u tp u t e n a b le
1 : e n a b le
0 : d is a b le
1 /2 B ia s C O M 3 o u tp u t e n a b le
1 : e n a b le
0 : d is a b le
L C D e n a b le /d is a b le C o n tr o l
1 : e n a b le
0 : d is a b le
S e le c t r e s is to r fo r R ty p e L C D b ia s c u r r e n t
1 : 2 x 5 0 k W ( 1 /2 b ia s ) , IB IA S = 5 0 m A a t V D D = 5 V
0 : 2 x 1 0 0 k W ( 1 /2 b ia s ) , IB IA S = 2 5 m A a t V D D = 5 V
N o t im p le m e n te d , r e a d a s " 0 "
LCD Control Register
Rev. 1.10
18
November 5, 2008
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