HT46R92 Ver la hoja de datos (PDF) - Holtek Semiconductor
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HT46R92 Datasheet PDF : 61 Pages
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HT46R92
Programming Considerations
Within the user program, one of the first things to con-
sider is port initialisation. After a reset, all of the I/O data
(except PC) and port control registers will be set high.
This means that all of the PC, PD and PE output pins will
be in a output floating condition. Also all the PA and PB
I/O pins will default to an input state, the level of which
depends on the other connected circuitry and whether
pull-high options have been selected. If the port control
registers, PAC and PBC, are then programmed to setup
some pins as outputs, these output pins will have an ini-
tial high output value unless the associated port data
registers, PA and PB, are first programmed. Selecting
which pins are inputs and which are outputs can be
achieved byte-wide by loading the correct values into
the appropriate port control register or by programming
individual bits in the port control register using the ²SET
[m].i² and ²CLR [m].i² instructions. Note that when using
these bit control instructions, a read-modify-write opera-
tion takes place. The microcontroller must first read in
the data on the entire port, modify it to the required new
bit values and then rewrite this data back to the output
ports.
Port A has the additional capability of providing wake-up
functions. When the device is in the Power Down Mode,
various methods are available to wake the device up.
One of these is a high to low transition of any of the Port
A pins. Single or multiple pins on Port A can be setup to
have this function.
D a ta B u s
W r ite C o n tr o l R e g is te r
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P W M o r B Z /B Z
R e a d D a ta R e g is te r
S y s te m W a k e - u p ( P A o n ly )
T M R fo r P A 2 o n ly
C o n tr o l B it
DQ
CK Q
S
P u ll- H ig h
O p tio n
D a ta B it
D
Q
CK Q
S
M
U
X
M
U
X
P W M or
B Z /B Z O p tio n
W a k e - u p O p tio n
PA Input/Output Ports
V DD
P A 0 /B Z
P A 1 /B Z
P A 2 /T M R
PA3
P A 4 /P W M 0
P A 5 /P W M 1
PA6
PA7
C o n tr o l B it
V DD
D a ta B u s
DQ
W r ite C o n tr o l R e g is te r
C h ip R e s e t
CK Q
S
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
D a ta B it
DQ
CK Q
S
LC D E N
R e a d D a ta R e g is te r
T o A /D C o n v e rte r
PCR2
PCR1
PCR0
M
U
X
A n a lo g
In p u t
S e le c to r
A C S 2~A C S 0
PB Input/Output Ports
P B 0 /A N 0
P B 1 /A N 1
P B 2 /A N 2
P B 3 /A N 3
P B 4 /A N 4
P B 5 /A N 5
PB6
PB7
Rev. 1.10
16
November 5, 2008
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