HT46R652-100 Ver la hoja de datos (PDF) - Holtek Semiconductor

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HT46R652-100

A/D with LCD Type 8-Bit OTP MCU

Holtek Semiconductor 

D a ta B u s

W r ite C o n tr o l R e g is te r

C h ip R e s e t

C o n tr o l B it

PU

DQ

CK Q

S

R e a d C o n tr o l R e g is te r

W r ite D a ta R e g is te r

P A 0 /P A 1 /P A 3 /P C 0 ~ P C 7 /P D 0 ~ P D 7

B Z /B Z /P F D /P W M 0 ~ P W M 7 /P W M 8 ~ P W M 1 5

R e a d D a ta R e g is te r

S y s te m W a k e -u p

( P A o n ly )

T M R 0 fo r P A 4 o n ly

IN T 0 fo r P A 5 o n ly

IN T 1 fo r P A 6 o n ly

T M R 1 fo r P A 7 o n ly

D a ta B it

DQ

CK Q

S

M

U

X

M

U

X

PFD EN

(P A 3 )

O P 0~O P 7

Input/Output Ports

HT46R652

V DD

P A 0 /B Z

P A 1 /B Z

PA2

P A 3 /P F D

P A 4 /T M R 0

P A 5 /IN T 0

P A 6 /IN T 1

P A 7 /T M R 1

P B 0 /A N 0 ~ P B 7 /A N 7

P C 0 /P W M 0 ~ P C 7 /P W M 7

P D 0 /P W M 8 ~ P D 7 /P W M 1 5

tion timer. If the pins are setup as inputs then they will al-

ways retain their input function. Once the BZ/BZ

configuration option is selected, the buzzer output sig-

nal is controlled by the PA0/PA1 data register.

The PA0/PA1 pins I/O functions are shown in the table.

PA0 I/O

I I OOOOOOOO

PA1 I/O

I O I I I OOOOO

PA0 Mode

XXCBBCBBBB

PA1 Mode

XCXXXCCCBB

PA0 Data

PA1 Data

X X D 0 1 D0 0 1 0 1

X D X X X D1 D D X X

PA0 Pad Status I I D 0 B D0 0 B 0 B

PA1 Pad Status I D I I I D1 D D 0 B

Note:

²I² input; ²O² output; ²D, D0, D1² Data

²B² buzzer option, BZ or BZ

²X² don¢t care; ²C² CMOS output

The PB port is also used for the A/D converter inputs.

The PWM outputs are shared with pins PC0~PC7 and

PD0~PD7. If the PWM function is enabled, the

PWM0~PWM15 outputs will appear on pins PC0~PC7

and PD0~PD7, if PC0~PC7 and PD0~PD7 are setup as

outputs. Writing a ²1² to the PC0~PC7 and PD0~PD7

data registers will enable the PWM output function while

writing a ²0² will force PC0~PC7 and PD0~PD7 to re-

main at a ²0²level. The I/O functions of PC0~PC7 and

PD0~PD7 are shown in the table.

I/O

I/P

O/P

I/P

Mode (Normal) (Normal) (PWM)

PC0~PC7, Logical Logical Logical

PD0~PD7 Input Output Input

O/P

(PWM)

PWM0~

PWM15

Any unused pins must be carefully managed to ensure

that there are no floating input lines which will result in in-

creased power consumption. It is therefore recom-

mended that any unused pins are setup as outputs or

connected to a pull-high resistor if setup as inputs.

The definitions of the PFD control signals and the PFD

output frequencies are listed in the following table.

Timer PA3 PA3

Timer Preload Data Pad

Value Register State

PFD

Frequency

OFF

X

0

0

X

OFF

X

1

U

X

ON

N

0

0

X

ON

N

1

PFD fTMR/[2´(M-N)]

Note:

²X² stands for unused

²U² stands for unknown

²M² is ²65536² for PFD0 or PFD1

²N² is the timer/event counter preload value

²fTMR² is the input clock frequency for the

timer/event counter

Rev. 1.00

21

December 19, 2006

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