HT46R652
Timer/Event Counter
Two timer/event counters, Timer/Event Counter 0 and
Timer/Event Counter,1 are implemented within the
microcontroller. Timer/Event Counter 0 is a 16-bit pro-
grammable count-up counter whose clock may come
from an external or internal source. The internal clock
source will come from fSYS. Timer/Event Counter 1 is
also a 16-bit programmable count-up counter whose
clock may come from an external source or an internal
source. The internal clock source comes from fSYS/4 or
a 32768Hz source, selected by a configuration option.
The external clock input allows the user to count exter-
nal events, measure time intervals or pulse widths, or to
generate an accurate time base.
There are three registers associated with Timer/Event
Counter 0; TMR0H, TMR0L and TMR0C, and another
three for Timer/Event Counter 1; TMR1H, TMR1L and
TMR1C. Writing to TMR0L and TMR1L will only put the
written data into an internal lower-order byte buffer
(8-bit) while writing to TMR0H and TMR1H will transfer
the specified data and the contents of the lower-order
byte buffer to the TMR0H/TMR1H and TMR0L/TMR1L
registers. The Timer/Event Counter 0/1 preload register
is changed with each TMR0H/TMR1H write operations.
Reading TMR0H/TMR1H will latch the contents of
TMR0H/TMR1H and TMR0L/TMR1L counters to the
destination and the lower-order byte buffer, respectively.
Reading TMR0L/TMR1L will only read the contents of
the lower-order byte buffer. The TMR0C and TMR1C
registers are the Timer/Event Counter control registers,
which control the operating mode, the timer enable or
disable and the active edge type.
The T0M0, T0M1 and T1M0, T1M1 bits define the timer
operational mode. The event count mode is used to
count external events, which requires that the clock
source comes from an external TMR0 or TMR1 pin. The
timer mode functions as a normal timer with the clock
source coming from the internally selected clock source.
The pulse width measurement mode can be used to
count the high or low level duration of an external signal
on pin TMR0 or TMR1, with the count value based on
the internally selected clock source.
In the event count or timer mode, the timer/event coun-
ter starts counting from the current contents in the
fS Y S
8 - s ta g e P r e s c a le r
fIN T
8 -1 M U X
T0P S C 2~T0P S C 0 TM R 0
T0M 1
T0M 0
T0E
L o w B y te
B u ffe r
1 6 - B it
P r e lo a d R e g is te r
D a ta B u s
R e lo a d
T0M 1
T0M 0
T0O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
H ig h B y te L o w B y te
1 6 - B it T im e r /E v e n t C o u n te r
PFD 0
O v e r flo w to In te r r u p t
Timer/Event Counter 0
D a ta B u s
fS Y S /4
M
U
32768H z X
T1S
f IN T
TM R 1
T1M 1
T1M 0
T1E
L o w B y te
B u ffe r
1 6 - B it
P r e lo a d R e g is te r
R e lo a d
T1M 1
T1M 0
T1O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
H ig h B y te L o w B y te
1 6 - B it T im e r /E v e n t C o u n te r
PFD 1
Timer/Event Counter 1
O v e r flo w to In te r r u p t
PFD 0
PFD 1
M
U
1 /2
PFD
X
P A 3 D a ta C T R L
P F D S o u r c e O p tio n
PFD Source Option
Rev. 1.00
18
December 19, 2006