HT46R54A Ver la hoja de datos (PDF) - Holtek Semiconductor

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HT46R54A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R53A/HT46R54A

The WDT time-out during HALT differs from other chip

reset conditions, for it can perform a ²warm reset² that

resets only the Program Counter and SP, leaving the

other circuits at their original state. Some registers re-

main unaffected during any other reset conditions. Most

registers are reset to the ²initial condition² when the re-

set conditions are met. Examining the PDF and TO

flags, the program can distinguish between different

²chip resets².

TO PDF

RESET Conditions

0 0 RES reset during power-up

u u RES reset during normal operation

0 1 RES wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² stands for ²unchanged²

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem reset (power-up, WDT time-out or RES reset) or the

system awakes from the HALT state. When a system re-

set occurs, the SST delay is added during the reset pe-

riod. Any wake-up from the HALT will enable the SST

delay. An extra option load time delay is added during

system reset (Power-up, WDT time-out at normal mode

or RES reset).

The functional unit chip reset status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler, Divider Cleared

WDT

Clear. After master reset,

WDT begins counting

Timer/Event Counter Off

Input/Output Ports Input mode

Stack Pointer

Points to the top of the stack

V DD

0 .0 1 m F *

100kW

RES

10kW

0 .1 m F *

Reset Circuit

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

VDD

RES

S S T T im e - o u t

tS S T + tO P D

C h ip R e s e t

Reset Timing Chart

H A LT

W DT

W DT

T im e - o u t

R eset

RES

E x te rn a l

O SC1

SST

1 0 - b it R ip p le

C o u n te r

W a rm R e s e t

C o ld

R eset

P o w e r - o n D e te c tio n

Reset Configuration

Rev. 1.00

13

August 24, 2006

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