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HT46R51A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R51A/HT46R52A

Bit No.

0

1

2

3

4

5

6

7

Label

EMI

EEI

ETI

EADI

EIF

TF

ADF

¾

Function

Controls the master (global) interrupt (1= enable; 0= disable)

Controls the external interrupt (1= enable; 0= disable)

Controls the Timer/Event Counter interrupt (1= enable; 0= disable)

Control the A/D converter interrupt (1= enable; 0= disable)

External interrupt request flag (1= active; 0= inactive)

Internal Timer/Event Counter request flag (1= active; 0= inactive)

A/D converter request flag (1= active; 0= inactive)

For test mode used only.

Must be written as ²0²; otherwise may result in unpredictable operation.

INTC (0BH) Register

EMI, EEI, ETI, and EADI are used to control the en-

abling/disabling of interrupts. These bits prevent the re-

quested interrupt from being serviced. Once the

interrupt request flags (TF, EIF, and ADF) are set, they

will remain in the INTC register until the interrupts are

serviced or cleared by a software instruction.

It is recommended that a program does not use the

²CALL subroutine² within the interrupt subroutine. Inter-

rupts often occur in an unpredictable manner or need to

be serviced immediately in some applications. If only one

stack is left and enabling the interrupt is not well con-

trolled, the original control sequence will be damaged

once the ²CALL² operates in the interrupt subroutine.

Oscillator Configuration

There are two oscillator circuits in the microcontroller.

V DD

O SC1

470pF

O SC1

O SC2

C r y s ta l O s c illa to r

fS Y S /4

O SC2

R C O s c illa to r

System Oscillator

Both of them are designed for system clocks, namely

the external RC oscillator and the external Crystal oscil-

lator, which are determined by options. No matter what

oscillator type is selected, the signal provides the sys-

tem clock. The HALT mode stops the system oscillator

and ignores an external signal to conserve power.

If an RC oscillator is used, an external resistor between

OSC1 and VSS is required and the resistance must

range from 24kW to 1MW. The system clock, divided by

4, is available on OSC2 with pull-high resistor, which

can be used to synchronize external logic. The RC os-

cillator provides the most cost effective solution.

However, the frequency of oscillation may vary with

VDD, temperatures and the chip itself due to process

variations. It is therefore not suitable for timing sensitive

operations where an accurate oscillator frequency is de-

sired.

If the Crystal oscillator is used, a crystal across OSC1

and OSC2 is needed to provide the feedback and phase

shift required for the oscillator, and no other external

components are required. Instead of a crystal, a resona-

tor can also be connected between OSC1 and OSC2 to

get a frequency reference, but two external capacitors in

OSC1 and OSC2 are required (If the oscillator can be

disabled by options to conserve power).

The WDT oscillator is a free running on-chip RC oscillator,

and no external components are required. Even if the sys-

tem enters the power down mode, the system clock is

stopped, but the WDT oscillator still works with a period of

approximately 65ms at 5V. The WDT oscillator can be dis-

abled by option to conserve power.

Watchdog Timer - WDT

The clock source of the WDT is implemented by a dedi-

cated RC oscillator (WDT oscillator) or instruction clock

(system clock divided by 4) decided by options. This

timer is designed to prevent a software mal-function or

sequence jumping to an unknown location with unpre-

dictable results. The watchdog timer can be disabled by

an option. If the watchdog timer is disabled, all the exe-

cutions related to the WDT result in no operation.

The WDT clock (fS) is further divided by an internal

counter to give longer watchdog time-outs. The division

ratio is fixed by an internal counter which gives a 215

fixed division ratio.

Once an internal WDT oscillator (RC oscillator with pe-

riod of 65ms normally) is selected, it is divided by 216 to

get the time-out period of approximately 4.3s. This

time-out period may vary with temperature, VDD and

process variations.

Rev. 1.30

10

March 6, 2009

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