46R01A3 Ver la hoja de datos (PDF) - Holtek Semiconductor
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46R01A3 Datasheet PDF : 58 Pages
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HT46R01A
An external clock source is used when the timer is in the
event counting mode, the clock source being provided
on an external timer pin TMR0, depending upon which
device and which timer is used. Depending upon the
condition of the T0E bit, each high to low, or low to high
transition on the external timer pin will increment the
counter by one.
Timer Registers - TMR0
The timer registers are special function registers located
in the Special Purpose Data Memory and is the place
where the actual timer value is stored. This register is
known as TMR0. The value in the timer registers in-
creases by one each time an internal clock pulse is re-
ceived or an external transition occurs on the external
timer pin. The timer will count from the initial value loaded
by the preload register to the full count of FFH at which
point the timer overflows and an internal interrupt signal is
generated. The timer value will then be reset with the ini-
tial preload register value and continue counting.
Note that to achieve a maximum full range count of FFH,
the preload register must first be cleared to all zeros. It
should be noted that after power-on, the preload regis-
ters will be in an unknown condition. Note that if the
Timer/Event Counters are in an OFF condition and data
is written to their preload registers, this data will be im-
mediately written into the actual counter. However, if the
counter is enabled and counting, any new data written
into the preload data registers during this period will re-
main in the preload registers and will only be written into
the actual counter the next time an overflow occurs.
Timer Control Registers - TMR0C
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of their respective control register.
The Timer Control Register is known as TMR0C. It is the
Timer Control Register together with its corresponding
timer registers that control the full operation of the
Timer/Event Counters. Before the timers can be used, it
is essential that the appropriate Timer Control Register
is fully programmed with the right data to ensure its cor-
rect operation, a process that is normally carried out
during program initialisation.
To choose which of the three modes the timer is to oper-
ate in, either in the timer mode, the event counting mode
or the pulse width measurement mode, bits 7 and 6 of
the Timer Control Register, which are known as the bit
pair T0M1/T0M0, must be set to the required logic lev-
els. The timer-on bit, which is bit 4 of the Timer Control
Register and known as T0ON, provides the basic on/off
control of the respective timer. Setting the bit high allows
the counter to run, clearing the bit stops the counter. Bits
0~2 of the Timer Control Register determine the division
ratio of the input clock prescaler. The prescaler bit set-
tings have no effect if an external clock source is used. If
the timer is in the event count or pulse width measure-
ment mode, the active transition edge level type is se-
lected by the logic level of bit 3 of the Timer Control
Register which is known as T0E.
b7
b0
T0M 1 T0M 0 T0S T0O N
T0E
T0P S C 2 T0P S C 1 T0P S C 0
T im e r /E v e n t C o u n te r C o n tr o l R e g is te r
TM R 0C
T im e r p r e s c a le r r a te s e le c t
T0P S C 2 T0P S C 1 T0P S C 0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
T im e r R a te
1 :1
1 :2
1 :4
1 :8
1 :1 6
1 :3 2
1 :6 4
1 :1 2 8
E v e n t C o u n te r a c tiv e e d g e s e le c t
1 : c o u n t o n fa llin g e d g e
0 : c o u n t o n r is in g e d g e
P u ls e W id th M e a s u r e m e n t a c tiv e e d g e s e le c t
1 : s ta r t c o u n tin g o n r is in g e d g e , s to p o n fa llin g e d g e
0 : s ta r t c o u n tin g o n fa llin g e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r c o u n tin g e n a b le
1 : e n a b le
0 : d is a b le
T im e r c lo c k s o u r c e
1:R TC
0 : fS Y S
O p e r a tin g m o d e s e le c t
T0M 1
0
0
1
1
T0M 0
0
1
0
1
n o m o d e a v a ila b le
e v e n t c o u n te r m o d e
tim e r m o d e
p u ls e w id th m e a s u r e m e n t m o d e
Rev. 1.10
18
August 13, 2008
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