48R01A1 Ver la hoja de datos (PDF) - Holtek Semiconductor
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48R01A1 Datasheet PDF : 49 Pages
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HT48R01A
b7
b0
B Z E N 1 B Z E N 0 Q O S C C L K M O D S y s te m C o n tr o l R e g is te r C T R L 0
S y s te m c lo c k m o d e s e le c tio n
0 : h ig h s p e e d - In te r n a l R C a s s y s te m c lo c k
1 : lo w s p e e d - R T C a s s y s te m c lo c k , In te r n a l R C o s c illa to r s to p p e d
N o te th a t th e s e s e le c tio n s a r e o n ly v a lid if th e o s c illa to r c o n fig u r a tio n
o p tio n s h a v e s e le c te d th e In te r n a l R C + R T C a s th e s y s te m c lo c k
R T C o s c illa to r q u ic k s ta r t- u p fu n c tio n
0 : q u ic k s ta r t- u p
1 : s lo w s ta r t- u p
B Z E N [1 :0 ] = B Z , B Z
0 0 : b o th d is a b le
0 1 : re s e rv e
1 0 : B Z o n ly e n a b le
1 1 : B Z a n d B Z e n a b le
N o t im p le m e n te d , r e a d a s " 0 "
System Control Register - CTRL0
b7
IN T E S 1 IN T E S 0
b0
W D T E N 3 W D T E N 2 W D T E N 1 W D T E N 0 S y s te m C o n tr o l R e g is te r C T R L 1
W D T fu n c tio n
1 0 1 0 d is a b le
X X X X o th e r v a lu e s - e n a b le
N o t im p le m e n te d , r e a d a s " 0 "
E x te r n a l in te r r u p t e d g e tr ig g e r ty p e
IN T E S 1 IN T E S 0
0
0
d is a b le
0
1
r is in g e d g e tr ig g e r
1
0
fa llin g e d g e tr ig g e r
1
1
d u a l e d g e tr ig g e r
System Control Register - CTRL1
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. There are seven I/O pins whose input or
output designation is under user program control and an
additional input pin. Additionally, as there are pull-high
resistor and wake-up software configurations for each
pin, the user is provided with an I/O structure to meet the
needs of a wide range of application possibilities.
Each device has a single I/O port known as Port A,
which has a corresponding data register known as PA.
This register is mapped to the Data Memory with an ad-
dress as shown in the Special Purpose Data Memory ta-
ble. Seven of these I/O lines can be used for input and
output operations and one line as an input only. For in-
put operation, these ports are non-latching, which
means the inputs must be ready at the T2 rising edge of
instruction ²MOV A,[m]², where m denotes the port ad-
dress. For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an exter-
nal resistor. To eliminate the need for these external re-
sistors, I/O pins PA0~PA6, when configured as an input
have the capability of being connected to an internal
pull-high resistor. These pull-high resistors are
selectable via a register known as PAPU, located in the
Data Memory. The pull-high resistors are implemented
using weak PMOS transistors.
Port A Wake-up
If the HALT instruction is executed, the device will enter
the Power Down Mode, where the system clock will stop
resulting in power being conserved, a feature that is im-
portant for battery and other low-power applications.
Various methods exist to wake-up the microcontroller,
one of which is to change the logic condition on one of
the PA0~PA7 pins from high to low. After a HALT instruc-
tion forces the microcontroller into entering the Power
Down Mode, the processor will remain idle or in a
low-power state until the logic condition of the selected
wake-up pin on Port A changes from high to low. This
function is especially suitable for applications that can
be woken up via external switches. Note that pins PA0 to
PA7 can be selected individually to have this wake-up
feature using an internal register known as PAWK, lo-
cated in the Data Memory.
Rev. 1.10
14
August 4, 2008
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