HT47R20A-1 Ver la hoja de datos (PDF) - Holtek Semiconductor
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HT47R20A-1 Datasheet PDF : 41 Pages
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S1
S y s te m C lo c k
S2
S y s te m C lo c k /4
S3
R T C O u tp u t
HT47R20A-1/HT47C20-1
T im e r A
O V B /O V A = 0
TO N
T im e r B
O V B /O V A = 1
In te rru p t
R esetT O N
S 12
S4
S5
S6
IN 0
CS0
C R T0
S7
S8
RS0
R T0
S 13
S9
S 10
S 11
IN 1
CS1
RS1
R T1
TN 2 TN 1 TN 0 S1 S2 S3
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
1
O th e r
0
0
0
N o te : 0 = o ff, 1 = o n
M 3 M 2 M 1 M 0 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
1
1
0
0
1
0
1
1
0
0
0
0
0
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
N o te : 0 = o ff, 1 = o n
RC Type A/D Converter
Input/Output Ports
There are 8-bit bidirectional input/output port and 4-bit
input port in the HT47R20A-1/HT47C20-1, labeled PA
and PB which are mapped to the data memory of [12H]
and [14H] respectively. The high nibble of the PA is
NMOS output and input with pull-high resisters. The low
nibble of the PA can be used for input/output or output
operation by selecting NMOS or CMOS output by op-
tions. Each bit on the PA can be configured as a
wake-up input, and the low nibble of the PA with or with-
out pull-high resistor by options. PB can only be used for
input operation, and each bit is with pull high resistor.
Both are for the input operation, these ports are
non-latched, that is, the inputs should be ready at the T2
rising edge of the instruction ²MOV A, [m]² (m=12H or
14H). For PA output operation, all data are latched and
remain unchanged until the output latch is rewritten.
When the structures of PA are open drain NMOS type, it
should be noted that, before reading data from the pads,
a ²1² should be written to the related bits to disable the
NMOS device. That is done first before executing the in-
struction ²MOV A, 0FFH² and ²MOV [12H], A² to disable
related NMOS device, and then ²MOV A, [12H]² to get
stable data.
After chip reset, these input lines remain at a high level
or are left floating (by ROM code option).
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or to the accumulator. Each bit of the PA output
latches can not use these instruction, which may
change the input lines to output lines (when input line is
at low level).
Rev. 1.80
20
June 23, 2008
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