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HSP45240

Address Sequencer

Intersil 

HSP45240

Processor Interface

The Processor Interface consists of a 10 pin microprocessor

interface and a register bank which holds configuration data.

The data is loaded into the register bank by first writing the

register address to the processor Interface and then writing

the data. An auto address increment mode is provided so that

a base address may be written followed by a number of data

writes.

The microprocessor interface consists of a 7 bit data bus (D0-

6), a one bit address select (A0) to specify D0-6 as either

address or data, a write input (WR) to latch data into the Pro-

cessor Interface, and a chip select input (CS) to enable writing

to the interface. The Processor Interface input is decoded as

either data or address as shown by the bit map in Table 1.

TABLE 1.

A0 D6 D5 D4 D3 D2 D1 D0

REGISTER ADDRESSES

Switch Output Registers. 1 x 0 n n n n n

Sequencer Starting

Address.

1x1000nn

Sequencer Block Size. 1 x 1 0 0 1 n n

Sequencer Number of

Blocks.

1x1010nn

Sequencer Block.

1x1011nn

Address Increment.

Sequencer Address.

1x1100nn

Increment.

Mode Control.

1x110100

Test Control.

1x110101

Start Delay Control.

1x110110

Address Sequencer

“START”.

1x 1 1 1 1 1 1

DATA WORDS

Current Address Data. 0 0 n n n n n n

(No Address Increment).

Current Address Data

(Address Increment).

01 n n n n n n

NOTES:

1. Table 1 “x” means “don’t care”, and “n” denotes bits which are de-

coded as an address in address registers and data in data registers.

2. When WR transitions “high” to write the Sequencer “Start” address

(1x111111), it must remain high until after a rising edge of clock.

Otherwise, the sequencer “start” signal will not be generated.

The register bank consists of a series of 6-bit registers which

may be addressed individually as shown in Table 1. The data in

these registers is down loaded into configuration registers in the

Start Circuitry, Sequence Generator, and Crosspoint Switch

when an address sequence is initiated by the internal START

signal (see Start Circuitry). This double buffered architecture

allows new configuration data to be down loaded to the Proces-

sor Interface while an address sequence is being completed

using previous configuration data.

The register bank has five sets of four registers which con-

tain address generation parameters. These parameters

include: Address Start, Block Size, Number of Blocks, Block

Increment, and Address Increment. Each register set maps

to one of five 24-bit configuration registers in the Sequence

Generator block (see Sequence Generator). The mapping of

the 6-bit registers in the register bank to the 24-bit configura-

tion registers is determined by the 2 LSBs of the register

address. The higher the value of the 2 LSBs the higher the

relative mapping of the 6-bit register to the 24-bit register.

For example, if the 2 LSBs of the register address are both

0, the register contents will map to the 6 LSBs of the configu-

ration register.

The register bank has 24 registers which contain the data for

Cross point Switch I/O mapping. These registers are

accessed via the 5 LSBs of the address for the Crosspoint

Mapping registers in Table 1. A value from 0 to 23 accesses

the mapping registers for OUTO-23 respectively. A value

greater than 23 is ignored. The output bit represented by a

particular register is mapped to the input by the 6-bit value

loaded into the register. If the value loaded into the register

exceeds 23, the corresponding output bit will be “0”. For

example, if the 5 LSBs of the Crosspoint Mapping address

are equal to 3, and the valued loaded into the register

accessed by this address is equal to 23, OUT3 would be

mapped to the MSB of the sequence generator output.

After a reset, the Mode Control, Test Control, and Start

Delay registers are reset as described in the section describ-

ing each register’s bit map; the Crosspoint Mapping registers

are reset to a 1:1 crosspoint switch mapping; the registers

which hold the five address generation parameters are not

affected.

To save the user the expense of alternating between

address and data writes, an auto address increment mode is

provided. The address increment mode is invoked by per-

forming data writes with a “1” in the D6 location of the data

word as shown in Table 1. For example, the crosspoint

switch could be configured by 25 writes to the Processor

Interface (one write for the starting address of the crosspoint

mapping registers followed by 24 data writes to those regis-

ters).

Mode Control Register

The Mode Control Register is used to control the operation

of the sequence generator. In addition, it also controls the

output delay between the MSW and the LSW of OUTO-23.

The following tables illustrate the structure of the mode con-

trol register.

TABLE 2. MODE CONTROL REGISTER FORMAT

ADDRESS LOCATION: 1x11O1OO

D5

D4

D3

D2

D1

D0

OD2

OD1

OD0

DS

M1

M0

6

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