INA-12063 Ver la hoja de datos (PDF) - HP => Agilent Technologies
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INA-12063 Datasheet PDF : 24 Pages
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well as to ensure that the perfor-
mance goals in Step 1 will be met.
Step 10. Build and Test
The final step is to fabricate
circuit boards and assemble
amplifiers for testing and verifica-
tion of performance. Some
adjustment in component values
and transmission lines may be
done at this step to allow for
imperfections in the computer
simulation. This completes the
amplifier design.
900 MHz LNA Design Example
As an application example, the
design of a low noise amplifier
stage for 900 MHz using the
INA-12063 will be described. This
amplifier design would be repre-
sentative for use in many low-
cost, battery power receiver
applications such as LNAs for
cellular telephones or 900 MHz
ISM/spread spectrum systems.
This example will follow the
above design sequence.
1. Performance goals. As a
receiver front end stage, the
primary design goals for this
example amplifier are: (1) noise
figure less than 2 dB, and, (2) a
input 3rd order intercept (IP3)
point of at least -10 dBm. Second-
ary goals are low output VSWR
and minimum DC current drain.
The resulting input VSWR and
stage gain will be accepted. Low
cost is always a design goal.
Results of this step:
Constrain:
NF ≤ 2 dB
Input IP3 ≥ -10 dBm
Low cost
Optimize:
Minimize output VSWR
Minimize DC power
Accept:
Gain
Input VSWR
2. Select bias conditions. For
this example, the supply voltage
is constrained by an assumed
battery supply of 3 volts, leaving
device current as the only remain-
ing bias variable. The current is
selected based on output power
which is driven by the IP3 require-
ment. The table of Electrical
Specifications provides a starting
point. Using the typical gain of
16␣ dB and a difference of 15 dB
between the output IP3 and P1dB,
the design goal of an input 3rd
order intercept point of -10 dBm
is translated to a 1-dB com-
pressed output power require-
ment of -9 dBm. Figure 8 indi-
cates a current of 2.5␣ mA will
meet this P1dB requirement with
adequate design margin.
Results of this step:
Bias: 3 volts, 2.5 mA
3. Choose PCB material. FR-4
with a thickness of 0.031 inches is
chosen as the printed circuit
board material. FR-4 meets the
requirement of low cost while
providing acceptable low loss
performance at 900 MHz.
A thickness of 0.031 inches is
suitable for the miniaturization of
microstriplines and thin enough
to allow for low inductance
ground vias. With a relative
dielectric constant (εr) of 4.8, the
width of a 50 Ω microstripline on
0.031 inch FR-4 is 0.056 inches,
which is a convenient size for
mounting chip components.
Results of this step:
PCB Material: 0.031-inch FR-4
4. Evaluate stability. Stability
factor is calculated from the set
of S-parameters closest to the
chosen bias condition, which in
this example is 3 volts and
2.5␣ mA. For the required accuracy
in the stability analysis, a short
length of transmission line
(0.030-inch long, 0.015-inch wide)
is added to connect the RF
ground pin (Pin 5) of the
INA-12063 to a 0.025-inch diam-
eter ground via.
Hewlett-Packard’s Touchstone
CAD program was used to
calculate the stability factor (K),
stability measure (B1), and gain
over the full S-parameter fre-
quency range of 0.1 to 3.1 GHz.
The results show a value of K<1
at 900 MHz, corresponding the
“Case 3” situation described in
the stability discussion in design
Step 4 above. To preserve NF,
the stabilizing resistor, R1, shown
in Figure 14, was added from the
output of the INA-12063 to
ground. Since the real part of the
output impedance of the INA-12
is >50␣ Ω, a resistor in the shunt
configuration is used to move the
overall impedance closer to 50␣ Ω.
RF
INPUT
INA-12063
GND 1
(PIN 5)
W = 0.015
L = 0.030
RF
OUTPUT
R1
0.025" DIA.
GROUND VIA
Figure 14. Stabilizing Resistor on
Output.
6-129
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