DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

HI1179JCQ Ver la hoja de datos (PDF) - Intersil

Número de pieza
componentes Descripción
Fabricante
HI1179JCQ Datasheet PDF : 14 Pages
First Prev 11 12 13 14
HI1179
Total Harmonic Distortion
This is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the measured input signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the 2nd and 3rd
harmonic component respectively to the RMS value of the
measured input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral compo-
nent. If the harmonics are buried in the noise floor it is the
largest peak.
Full Power Input Bandwidth
Full power bandwidth is the frequency at which the ampli-
tude of the digitally reconstructed output has decreased 3dB
below the amplitude of the input sine wave. The input sine
wave has a peak-to-peak amplitude equal to the reference
voltage. The bandwidth given is measured at the specified
sampling frequency.
Timing Definitions
Sampling Delay (tSD)
Sampling delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
This is the RMS variation in the sampling delay due to
variation of internal clock path delays.
Data Latency (tLAT)
After the analog sample is taken, the data on the bus is
available after 2.5 cycles of the clock. This is due to the
architecture of the converter where the data has to ripple
through the stages. This delay is specified as the data
latency. After the data latency time, the data representing
each succeeding sample is output at the following clock
pulse. The digital data lags the analog input by 2.5 cycles.
Output Data Delay (tD)
Output Data Delay is the delay time from when the data is
valid (rising clock edge) to when it shows up at the output
bus. This is due to internal delays at the digital output.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
4-1123

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]