HI-8588PST(2001) Ver la hoja de datos (PDF) - Holt Integrated Circuits
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HI-8588PST Datasheet PDF : 6 Pages
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HI-8588
FUNCTIONAL DESCRIPTION
RECEIVER
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each have series resistors, typi-
cally 35K ohms. They connect to level translators whose
resistance to Ground is typically 10K ohms. Therefore, any
series resistance added to the inputs will affect the voltage
translation.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the dif-
ferential signal is compared to levels derived from a di-
vider between VCC and Ground. The nominal settings cor-
respond to a One/Zero amplitude of 6.0V and a Null ampli-
tude of 3.3V.
The status of the ARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of theTestA and
TestB pins. If TestA and TestB are both One, then the re-
ceiver is powered down and the output pins float. The
powerdown does not disconnect the internal resistors at
the ARINC input.
RINA
RINB
ESD
PROTECTION
AND
TRANSLATION
ONE
NULL
ZERO
NULL
SQ
LATCH
R
SQ
LATCH
R
TEST
TEST
TESTA
TEST
TEST
TESTB
FIGURE 1 - RECEIVER BLOCK DIAGRAM
ROUTA
TESTA ' TESTB
ROUTB
TESTA ' TESTB
APPLICATION INFORMATION
Figure 2 shows a possible application of the
HI-8588 interfacing an ARINC receive channel
to the HI-6010 which in turn interfaces to an
8-bit bus.
1
2
6
8
7
4
3
5
1
6
7
8
2
3
45
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2
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