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HC-8382CM-01

ARINC 429 DIFFERENTIAL LINE DRIVER

Holt Integrated Circuits 

HI-8382, HI-8383

FUNCTIONAL DESCRIPTION

The SYNC and CLOCK inputs establish data synchronization

utilizing two AND gates, one for each data input. Each logic

input, including the power enable (STROBE) input, are

TTL/CMOS compatible. Besides reducing chip current drain,

STROBE also floats each output. However the overvoltage

fuses and diodes of the HI-8382 are not switched out.

Figure 1 illustrates a typical ARINC 429 bus application.

Three power supplies are necessary to operate the HI-8382;

typically +15V, -15V and +5V. The chip also works with ±12V

supplies. The +5V supply can also provide a reference

voltage that determines the output voltage swing. The

differential output voltage swing will equal 2VREF. If a value of

VREF other than +5V is needed, a separate +5V power supply

is required for pin V1.

With the DATA (A) input at a logic high and DATA (B) input at a

logic low, AOUT will switch to the +VREF rail and BOUT will

switch to the -VREF rail (ARINC HIGH state). With both data

input signals at a logic low state, the outputs will both switch to

0V (ARINC NULL state).

The driver output impedance, ROUT, is nominally 75 ohms.

The rise and fall times of the outputs can be calibrated through

the selection of two external capacitor values that are

connected to the CA and CB input pins. Typical values for

high-speed operation (100KBPS) are CA = CB = 75pF and for

low-speed operation (12.5 to 14KBPS) CA = CB = 500pF.

The driver can be externally powered down by applying a logic

high to the STROBE input pin. If this feature is not being used,

the pin should be tied to ground.

The CA and CB pins are inputs to unity gain amplifiers.

Therefore they must be allowed to swing to -5V. Provision to

switch capacitors must be done with analog switches that

allow voltages below their ground.

Both ARINC outputs of the HI-8382 are protected by internal

fuses capable of sinking between 800 - 900 mA for short

periods of time (125µs).

POWER SUPPLY SEQUENCING

The power supplies should be controlled to prevent large

currents during supply turn-on and turn-off. The recom-

mended sequence is +V followed by V1, always ensuring that

+V is the most positive supply. The -V supply is not critical

and can be asserted at any time.

+5V

+15V

DATA (A)

INPUTS

DATA (B)

VREF

V1

SYNC

CLOCK

+V

-V

STROBE

GND

CB

CA

AOUT

TO ARINC BUS

BOUT

-15V

Figure 1. ARINC 429 BUS APPLICATION

VREF +V CA

A OUT

DATA (A)

CLOCK

SYNC

DATA (B)

V1

STROBE

CURRENT

REGULATOR

LEVEL SHIFTER

AND SLOPE

CONTROL (A)

ROUT / 2

FA

OUTPUT

DRIVER (A)

LEVEL SHIFTER

AND SLOPE

CONTROL (B)

ROUT / 2

FB

OUTPUT

DRIVER (B)

Not included on HI-8383

OVER VOLTAGE

CLAMPS

RL

CL

GND -V CB

Figure 2. FUNCTIONAL BLOCK DIAGRAM

HOLT INTEGRATED CIRCUITS

2

BOUT

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