HI-565A(2002) Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Fabricante
HI-565A Datasheet PDF : 9 Pages
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HI-565A
R3
REF OUT VCC
100Ω
R4
100Ω
43
+
10V
-
HI-565A
I REF
REF 6 19.95K
IN
REF 5
GND
0.5mA
3.5K
+-
3K
BIP.
OFF. 8
5K
9.95K
DAC
IO
(4 x I REF
x CODE)
5K
2.5K
CODE
INPUT
7 12 24
MSB
-VEE PWR
GND
13
LSB
11
20V SPAN
10
10V SPAN
VO
C
9
DAC
OUT
-
+
R (SEE
TABLE 2)
FIGURE 2. BIPOLAR VOLTAGE OUTPUT
Settling Time
This is a challenging measurement, in which the result
depends on the method chosen, the precision and quality of
test equipment and the operating configuration of the DAC
(test conditions). As a result, the different techniques in use
by converter manufacturers can lead to consistently different
results. An engineer should understand the advantage and
limitations of a given test method before using the specified
settling time as a basis for design.
The previous approach calls for a strobed comparator to
sense final perturbations of the DAC output waveform. This
gives the LSB a reasonable magnitude (814µV for the
HI-565A), which provides the comparator with enough
overdrive to establish an accurate ±0.5 LSB window about the
final settled value. Also, the required test conditions simulate
the DACs environment for a common application - use in a
successive approximation A/D converter. Considerable
experience has shown this to be a reliable and repeatable
way to measure settling time.
The usual specification is based on a 10V step, produced by
simultaneously switching all bits from off-to-on (tON) or on-
to-off (tOFF). The slower of the two cases is specified, as
measured from 50% of the digital input transition to the final
entry within a window of ±0.5 LSB about the settled value.
Four measurements characterize a given type of DAC:
(a) tON, to final value +0.5 LSB
(b) tON, to final value -0.5 LSB
(c) tOFF, to final value +0.5 LSB
(d) tOFF, to final value -0.5 LSB
(Cases (b) and (c) may be eliminated unless the overshoot
exceeds 0.5 LSB). For example, refer to Figure 3 for the
measurement of case (d).
Procedure
As shown in Figure 3B, settling time equals tX plus the
comparator delay (tD = 15ns). To measure tX:
• Adjust the delay on generator No. 2 for a tX of several
microseconds. This assures that the DAC output has
settled to its final value.
• Switch on the LSB (+5V).
• Adjust the VLSB supply for 50% triggering at
COMPARATOR OUT. This is indicated by traces of
equal brightness on the oscilloscope display as shown
in Figure 3B. Note DVM reading.
• Switch the LSB to Pulse (P).
• Readjust the VLSB supply for 50% triggering as before,
and note DVM reading. One LSB equals one tenth the
difference in the DVM readings noted above.
• Adjust the VLSB supply to reduce the DVM reading by
5 LSBs (DVM reads 10X, so this sets the comparator to
sense the final settled value minus 0.5 LSB).
Comparator output disappears.
• Reduce generator No. 2 delay until comparator output
reappears, and adjust for “equal brightness”.
• Measure tX from scope as shown in Figure 3B. Settling
time equals tX + tD, i.e., tX + 15ns.
6
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