HEF4021BT Ver la hoja de datos (PDF) - NXP Semiconductors.
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HEF4021BT Datasheet PDF : 14 Pages
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NXP Semiconductors
HEF4021B
8-bit static shift register
VDD
CP INPUT
VM
VSS
tW
trec
VDD
PL INPUT
VM
VSS
tsu
VDD 90 %
Dn INPUT
VM
VSS
10 %
tf
th
tr
001aae612
Fig 6.
Set-up times and hold times are shown as positive values but may be specified as negative values;
Measurement points are given in Table 9.
Waveforms showing minimum pulse width and recovery time for PL; set-up and hold times for Dn to PL.
Table 9. Measurement points
Supply voltage
Input
VDD
5 V to 15 V
VM
0.5VDD
Output
VM
0.5VDD
VX
0.1VDD
VY
0.9VDD
VDD
VI
G
VO
DUT
RT
CL
001aag182
Fig 7.
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Test circuit
Table 10. Test data
Supply voltage
VDD
5 V to 15 V
Input
VI
VSS or VDD
tr, tf
≤ 20 ns
Load
CL
50 pF
HEF4021B_4
Product data sheet
Rev. 04 — 10 November 2008
© NXP B.V. 2008. All rights reserved.
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