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HEF4021BT Datasheet PDF : 14 Pages
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NXP Semiconductors
HEF4021B
8-bit static shift register
Table 3. Function table[1] …continued
Number of clock Inputs
transitions
CP
DS
PL
8
↑
X
L
↓
X
L
Parallel operation
X
X
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;
↑ = LOW to HIGH clock transition; ↓ = HIGH to LOW clock transition;
data n = data (HIGH or LOW) on the DS input at the nth ↑ CP transition.
Outputs
Q5
data 3
no change
D5
8. Limiting values
Q6
data 2
no change
D6
Q7
data 1
no change
D7
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDD
IIK
VI
IOK
II/O
IDD
Tstg
Tamb
Ptot
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
Tamb −40 °C to +125 °C
DIP16 package
SO16 package
P
power dissipation
per output
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
Min
−0.5
-
−0.5
-
-
-
−65
−40
[1] -
[2] -
-
9. Recommended operating conditions
Max
Unit
+18
V
±10
mA
VDD + 0.5 V
±10
mA
±10
mA
50
mA
+150
°C
+125
°C
750
mW
500
mW
100
mW
Table 5.
Symbol
VDD
VI
Tamb
∆t/∆V
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
ambient temperature
in free air
input transition rise and fall rate
VDD = 5 V
VDD = 10 V
VDD = 15 V
Min Typ Max
Unit
3
-
15
V
0
-
−40 -
VDD
V
+125 °C
-
-
3.75
ns/V
-
-
0.5
ns/V
-
-
0.08
ns/V
HEF4021B_4
Product data sheet
Rev. 04 — 10 November 2008
© NXP B.V. 2008. All rights reserved.
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