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HEF4021BT Datasheet PDF : 14 Pages
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NXP Semiconductors
HEF4021B
8-bit static shift register
6. Pinning information
6.1 Pinning
Fig 3. Pin configuration
HEF4021B
D7 1
Q5 2
Q7 3
D3 4
D2 5
D1 6
D0 7
VSS 8
16 VDD
15 D6
14 D5
13 D4
12 Q6
11 DS
10 CP
9 PL
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6.2 Pin description
Table 2. Pin description
Symbol
Pin
Q5 to Q7
2, 12, 3
D0 to D7
7, 6, 5, 4, 13, 14,15, 1
VSS
8
PL
9
CP
10
DS
11
VDD
16
Description
buffered parallel output from the last three stages
parallel data input
ground supply voltage
parallel load input
clock input (LOW-to-HIGH edge-triggered)
serial data input
supply voltage
7. Functional description
Table 3. Function table[1]
Number of clock Inputs
transitions
CP
DS
PL
Serial operation
1
↑
data 1
L
2
↑
data 2
L
3
↑
data 3
L
6
↑
X
L
7
↑
X
L
Outputs
Q5
Q6
Q7
X
X
X
X
X
X
X
X
X
data 1
X
X
data 2
data 1
X
HEF4021B_4
Product data sheet
Rev. 04 — 10 November 2008
© NXP B.V. 2008. All rights reserved.
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