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HEF4021BPN

8-bit static shift register

Philips Electronics 

Philips Semiconductors

8-bit static shift register

Product specification

HEF4021B

MSI

DESCRIPTION

The HEF4021B is an 8-bit static shift register

(parallel-to-serial converter) with a synchronous serial

data input (DS), a clock input (CP), an asynchronous active

HIGH parallel load input (PL), eight asynchronous parallel

data inputs (P0 to P7) and buffered parallel outputs from

the last three stages (05 to O7).

Each register stage is a D-type master-slave flip-flop with

a set direct/clear direct input. Information on P0 to P7 is

asynchronously loaded into the register while PL is HIGH,

independent of CP and DS. When PL is LOW, data on

DS is shifted into the first register position and all the data

in the register is shifted one position to the right on the

LOW to HIGH transition of CP. Schmitt-trigger action in the

clock input makes the circuit highly tolerant to slower clock

rise and fall times.

Fig.1 Functional diagram.

PINNING

PL

P0 to P7

DS

CP

O5 to O7

Fig.2 Pinning diagram.

HEF4021BP(N): 16-lead DIL; plastic

(SOT38-1)

HEF4021BD(F): 16-lead DIL; ceramic (cerdip)

(SOT74)

HEF4021BT(D): 16-lead SO; plastic

(SOT109-1)

( ): Package Designator North America

FAMILY DATA, IDD LIMITS category MSI

See Family Specifications

parallel load input

parallel data inputs

serial data input

clock input (LOW to HIGH edge-triggered)

buffered parallel outputs from the last three stages

January 1995

2

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