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HD404324 Ver la hoja de datos (PDF) - Renesas Electronics

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HD404324
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HD404324 Datasheet PDF : 96 Pages
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HD404328 Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as shown in table 4.
Table 4 Interrupt Enable Flag
IE
Interrupt Enabled/Disabled
0
Disabled
1
Enabled
External Interrupts (INT0, INT1): Specified by port mode register A (PMRA: $004).
External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): Set at the rising or falling
edges of the INT0 and INT1 inputs, as shown in table 5.
Table 5 External Interrupt Request Flags
IF0, IF1
0
1
Interrupt Request
No
Yes
IF0 is set at the falling edge of signals input to INT0, and IF1 is set at the rising and falling edges of signals
input to INT1. The INT1 interrupt edge is selected by the interrupt mode register (IMR: $010), as shown in
figure 9.
Interrupt mode register (IMR): $010
3
2
1
0 Initial value: 0000, R/W: W
INT1 detection edge selection
ZCD detection edge selection
IMR
Bit 3 Bit 2
0
0
1
0
1
1
ZCD Detection Edge
No detection
Falling-edge detection
Rising-edge detection
Double-edge detection
IMR
Bit 1 Bit 0
0
0
1
0
1
1
Figure 9 Interrupt Mode Register
INT1 Detection Edge
No detection
Falling-edge detection
Rising-edge detection
Double-edge detection
22

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