GL800HT25 Ver la hoja de datos (PDF) - GENESYS LOGIC

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Fabricante

GL800HT25

USB 2.0 UTMI Compliant Transceiver IP Core

GENESYS LOGIC 

GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core

5.1.2 Transmit Timing for Data Packet

CLK30

TXVLD

Data

TXRDY

DP/DM

PID

Data Data Data Data CRC CRC

SYNC

C C P PID Data Data Data Data CRC CRC EOP

Figure 5.2 - Timing Diagram of Transmit for Data Packet

The SIE negates TXVLD to complete a packet. Once negated, the Transmit State Machine will never reassert

TXRDY until after the EOP has been loaded into the Transmit Shift Register. Note that the UTM Transmit

State Machine can be ready to start another package immediately, however the SIE must confirm to the

minimum inter-packet delays identified in the USB 2.0 Specification.

5.2 Receive Operation

5.2.1 Receive State Diagram

!SYNC

HRST#

Reset

!RXACTV

!HRST#

RX Wait

Terminate

!RXACTV

!RXVLD

Strip EOP

SYNC Detected

Trip SYNC

Data

Rx Data

!RXACTV

EOP

!RXVLD

Detected

Abort 1

Idle

state

RXACTV

Data

RXVLD

!RXACTV

!RXVLD

SYNC

!Data

Data

RX Data Wait

Receive

Error

Error

RXERR

!RXERR

Abort 2

!RXVLD

!RXERR

!RXVLD

!Data

!Idle

state

Figure 5.3 - Receive State Diagram

©2000-2003 Genesys Logic Inc.—All rights reserved.

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