GL800HT25 Ver la hoja de datos (PDF) - GENESYS LOGIC

Número de pieza

componentes Descripción

Fabricante

GL800HT25

USB 2.0 UTMI Compliant Transceiver IP Core

GENESYS LOGIC 

GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core

D0~D15

DVDD0

DVDD1

DGND0~1

LINEST1

LINEST0

27~30,

33~40,

43~46

31

41

32,42

47

48

data for next transfer on the Data bus. If TXVLD is asserted and

TXRDY is negated, the SIE must hold the previously asserted data

on the Data bus. From the time TXVLD is negated, TXRDY is a

don’t care for the SIE.

B Data bus 0~15

P Positive digital supply (3.3V)

Positive digital supply

P UMC 0.35um sample : 3.3V

TSMC 0.25um sample : 2.5V

P Digital ground (0V)

O Line State. These signals reflect the current state of the single

ended receivers. They are combinatorial until a “usable” CLK30 is

available then they are synchronized to CLK30. They directly

reflect the current state of the DP (LineState[0]) and DM

(LineState[1]) signals:

O DM DP Description

0 1 0: SE0

0 1 1: ‘J’ State

1 0 2: ‘K’ State

1 1 3: SE1

Notation:

Type O

I

B

B/I

B/O

P

A

SO

pu

pd

odpu

Output

Input

Bi-directional

Bi-directional, default input

Bi-directional, default output

Power / Ground

Analog

Automatic output low when suspend

Internal pull up

Internal pull down

Open drain with internal pull up

©2000-2003 Genesys Logic Inc.—All rights reserved.

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