GL800HT25 Ver la hoja de datos (PDF) - GENESYS LOGIC
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GL800HT25 Datasheet PDF : 20 Pages
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GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core
DMH
AGND0~1
RREF
XO
XI
TEST0
OPMOD1
OPMOD0
RXACTV
RXERR
RXVLD
CLKOUT
TXVLD
VALIDH
TXRDY
10
11,16
12
14
15
17
18
19
20
21
22
23
24
25
26
B Negative USB Differential Data (High Speed)
P Analog ground (0V)
- 510 Ω reference resistor input
B Crystal output
I 12MHz crystal/oscillator input
I
(pd)
Test mode enable
I Operational mode. These signals select between various
(pu) operational modes:
[1] [0] Description
I
(pd)
0
0
1
0
1
0
0: Normal Operation
1: Non-Driving
2: Disable Bit Stuffing and NRZI encoding
1 1 3: Reserved
Receive Active, active high. Indicates that the receive state
machine has detected SYNC and is active. RXACTV is negated
after a Bit Stuff Error or an EOP is detected.
In HS mode, RXACTV must be negated no less than 3 and no
more than 8 CLKs after an Idle state is detected on the USB.
O And RXACTV must be negated for at least 1 CLK between
consecutive received packets.
In FS/FS only modes, RXACTV must be negated no more than 2
CLKs after a FS Idle state is detected on the USB. And RXACTV
must be negated for at least 4 CLKs between consecutive received
packets.
Receive Error, active high.
0: Indicates no error.
O
1: Indicates that a receive error has been detected.
This output is clocked with the same timing as the Data lines and
can occur at anytime during a transfer. If asserted, it will force the
negation of RXVLD on the next rising edge of CLK30.
Receive Data Valid, active high. Indicates that the Data bus has
O valid data. The Rx Register is full and ready to be unloaded. The
SIE is expected to latch the Data bus on the clock edge.
O
Clock. This 30MHz clock output is used for clocking receive and
transmit HS/FS 16-bit parallel data.
Transmit Valid, active high. Indicates that the Data bus is valid.
The assertion of Transmit Valid initiates SYNC on the USB. The
negation of Transmit Valid initiates EOP on the USB.
In HS mode, the SYNC pattern must be asserted on the USB
I between 8 and 16 bit times after the assertion of TXVLD is
detected by the Transmit State Machine.
In FS/ FS only Modes, the SYNC pattern must be asserted on the
USB no less than 1 CLK and no more than 5 CLKs after the
assertion of TXVLD is detected by the Transmit State Machine.
B Transmit/Receive Valid High, active high.
Transmit data ready, active high. If TXVLD is asserted, the SIE
must always have data available for clocking in to the TX Register
O
on the rising edge of CLK30. If TXVLD is true and TXRDY is
asserted at the rising edge of CLK30, the GL800HT25 will load
the data on the Data bus into the TX Register on the next rising
edge of CLK30, at that time, SIE should immediately present the
©2000-2003 Genesys Logic Inc.—All rights reserved.
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