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G121X1-L03

TFT LCD Tentative Specification

AZ Displays 

Issued Date: Feb. 9, 2009

Model No.: G121X1-L03

Tentative

6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

The input signal timing specifications are shown as the following table and timing diagram.

DCLK

Signal

Vertical Active Display Term

Horizontal Active Display Term

Item

Frequency

Period

Frame Rate

Total

Display

Blank

Total

Display

Blank

Symbol

Fc

Tc

Fr

Tv

Tvd

Tvb

Th

Thd

Thb

Min.

57.5

13.4

56

774

768

Tv-Tvd

1240

1024

Th-Thd

Typ.

64.9

15.4

60

806

768

38

1344

1024

320

Max.

74.4

17.3

75

848

768

Tv-Tvd

1464

1024

Th-Thd

Unit

MHz

ns

Hz

Th

Th

Th

Tc

Tc

Tc

Note

Tv=Tvd+Tvb

Th=Thd+Thb

Note：(1) Because this module is operated by DE only mode, Hsync and Vsync input signals should be

set to low logic level or ground. Otherwise, this module would operate abnormally.

INPUT SIGNAL TIMING DIAGRAM

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Version 0.0

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