PEF2466(2001) Ver la hoja de datos (PDF) - Infineon Technologies

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componentes Descripción

Fabricante

PEF2466
(Rev.:2001)

Four Channel Codec Filter with PCM and Microcontroller Interface SICOFI®4-µC

Infineon Technologies 

PEB 2466

PEF 2466

Functional Description

VIN1

VOUT1

PEB 2466, SICOFI4-µC

ADC

DAC

Hardware

Filters

VIN2

VOUT2

ADC

DAC

Hardware

Filters

VIN3

VOUT3

ADC

DAC

Hardware

Filters

VIN4

VOUT4

ADC

DAC

Hardware

Filters

MCLK

CHCLK1

CHCLK2

SIx_y

SOx_y

SBx_y

PLL,

Clocking

Signaling Interface

Programmable

Filters and Gain

Programmable

Filters and Gain

Programmable

Filters and Gain

Programmable

Filters and Gain

Digital Signal Processing

A-Law

or

µ-Law

A-Law

or

µ-Law

A-Law

or

µ-Law

A-Law

or

µ-Law

Compander

PCM-

Interface

with

Highway A

DXA

DRA

TCA#

FSC

PCLK

Time Slot

Assignment

Highway B

DXB

DRB

TCB#

Registers and CRAM

Serial Microcontroller Interface

INT34 INT12

DCLK CS# DIN DOUT

2466_205

Figure 4 SICOFI®4-µC Block Diagram

Figure 4 shows the functional blocks and the interface pins of the SICOFI®4-µC:

• Four independent bi-directional voice channels;

• Oversampling sigma-delta A/D and D/A converters with excellent resolution, dynamic

range, linearity, accuracy and signal-to-noise performance;

• Hardware filters for decimation and interpolation of the ADC and DAC bit stream, and

pre-processing of the voice data to reduce the load of the DSP;

• DSP core with programmable, channel-independent filter structures for impedance

matching, transhybrid balancing, frequency correction and level adjustments;

• Configurable A-Law or µ-Law compressor and expander units;

• Two PCM ports with data rates from 128 kbps to 8 Mbps per highway;

• Programmable time slot assignment for each channel;

• twenty-eight signaling input and output pins, accessible through registers;

• On-chip PLL for an internal 16.384 MHz clock;

• Two programmable versatile clock outputs;

• Eight common configuration registers (XR-Registers) affecting all four channels;

• Four sets of six channel-specific registers (CR-Registers); and

• Coefficient RAM (CRAM) for filter coefficients storage for each channel.

Hardware Reference Manual

11

2001-02-20

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