PEB2466HV2.2(2001) Ver la hoja de datos (PDF) - Infineon Technologies

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componentes Descripción

Fabricante

PEB2466HV2.2
(Rev.:2001)

Four Channel Codec Filter with PCM and Microcontroller Interface SICOFI®4-µC

Infineon Technologies 

PEB 2466

PEF 2466

Pin Descriptions

Pin Symbol Type Function

Ch.

Digital Ground

21 GNDD I Ground reference for all digital signals.

all

Internally isolated from GNDA1,2,3,4.

Master Clock Input

22 MCLK

I

1536, 2048, 4096 or 8192 kHz must be applied for any

operation (selected in Register XR5).

all

MCLK, PCLK, FSC must be synchronous.

23 RESET#

I

Reset Input

Forces the device to default setting mode; active low.

all

24 VDDD

I

Digital Supply Voltage

+5 V supply for digital circuits (use 100 nF blocking cap.).

all

Transmit Control Output A

25 TCA# O PCM Interface: active if data is transmitted via DXA;

all

active low, open drain.

26 DXA

Data Transmit to PCM-Highway A

O PCM Interface: PCM data for each channel is transmitted all

in 8-bit bursts every 125 µs.

27 DRA

Data Receive from PCM-Highway A

I PCM Interface: PCM data for each channel is received in all

8-bit bursts every 125 µs.

Transmit Control Output B

28 TCB# O PCM Interface: active if data is transmitted via DXB;

all

active low, open drain.

Data Transmit to PCM-highway B

29 DXB O PCM Interface: data for each channel is transmitted in all

8-bit bursts every 125 µs.

30 DRB

Data Receive from PCM-highway B

I PCM Interface: data for each channel is received in 8-bit all

bursts every 125 µs.

31 FSC

Frame Synchronization Clock

I 8 kHz; reference for individual time slots, indicates start of all

PCM frame; MCLK, PCLK, FSC must be synchronous.

32 PCLK

PCM Data Clock

I

128 to 8192 kHz; determines the rate at which PCM data

is shifted into or out of the PCM-ports.

all

MCLK, PCLK, FSC must be synchronous.

Hardware Reference Manual

7

2001-02-20

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