992215735011 Ver la hoja de datos (PDF) - Philips Electronics
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992215735011 Datasheet PDF : 17 Pages
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Philips Semiconductors
Frame Transfer CCD Image Sensor
Product specification
FTT1010-M
Pin configuration
The FTT1010-M is mounted in a Pin Grid Array (PGA) package with
76 pins in a 15x13 grid of 40.00 x 40.00 mm2. The position of pin A1
is marked with a gold dot on top of the package.
Symbol
VNS
VNS
VNS
VNS
VNS
VPS
SFD
SFS
VCS
OG
RD
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
SG
RG
OUT
NC
N substrate
N substrate
N substrate
N substrate
N substrate
P substrate
Source Follower Drain
Source Follower Source
Current Source
Output Gate
Reset Drain
Image Clock (Phase 1)
Image Clock (Phase 2)
Image Clock (Phase 3)
Image Clock (Phase 4)
Storage Clock (Phase 1)
Storage Clock (Phase 2)
Storage Clock (Phase 3)
Storage Clock (Phase 4)
Register Clock (Phase 1)
Register Clock (Phase 2)
Register Clock (Phase 3)
Summing Gate
Reset Gate
Output
Not connected
Name
The clock phases of quadrant W are internally connected to X, and
the clock phases of Y are connected to Z.
Pin # W
A12
D11
E11
E12
-
C11
A13
A10
A11
B13
B12
-
-
-
-
D13
C12
D12
C13
B9
B8
A8
B10
A9
B11
B7
Pin # X
A3
B2
D3
E2
E3
C3
A1
B5
A4
B1
B3
-
-
-
-
D1
C2
D2
C1
A6
A7
B6
A2
A5
B4
Pin # Y
J2
F3
-
-
-
G3
J1
J4
J3
H1
H2
F1
G2
F2
G1
-
-
-
-
H5
H6
J6
H4
J5
H3
H7
Pin # Z
F11
H12
J11
-
-
G11
J13
H9
J10
H13
H11
F13
G12
F12
G13
-
-
-
-
J8
J7
H8
J12
J9
H10
13 12 11 10 9 8 7 6 5 4 3 2 1
J
SFD SG VNS VCS RG C1 C2 C3 RG SFS VCS VNS SFD
J
H
OG VNS RD OUT SFS C3 NC C2 C1 SG OUT RD OG
H
G
A4 A2 VPS
F
A1 A3 VNS
TOP
VPS A2 A4
G
VNS A3 A1
F
Z
IMAGE
Y
W STORAGE
X
VNS VNS
E
D
B1 B3 VNS
C
B4 B2 VPS
FTT1010-M
VNS VNS
E
VNS B3 B1
D
VPS B2 B4
C
B
OG RD OUT SG C1 C2 NC C3 SFS OUT RD VNS OG
B
A
SFD VNS VCS SFS RG C3 C2 C1 RG VCS VNS SG SFD
A
13 12 11 10 9 8 7 6 5 4 3 2 1
Figure 13 - FTT1010-M pin configuration (top view)
1999 September
15
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