FOD8012 Ver la hoja de datos (PDF) - Fairchild Semiconductor
Número de pieza
componentes Descripción
Fabricante
FOD8012 Datasheet PDF : 12 Pages
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Switching Characteristics
TA = -40ºC to +110ºC, 3.0V ≤ VDD ≤ 5.5V, unless otherwise specified.
Apply over all recommended conditions, typical value is measured at VDD1 = VDD2 = +3.3V, TA=25ºC
Symbol
Parameter
Conditions
Min. Typ. Max.
Data Rate
15
Units
Mbit/s
tPHL
tPLH
PWD
tPSK(CC)
Propagation Delay Time
to Logic Low Output
Propagation Delay Time
to Logic High Output
Pulse Width Distortion,
| tPHL – tPLH |
Channel-Channel Skew
PW = 66.7ns, CL = 15pF
PW = 66.7ns, CL = 15pF
PW = 66.7ns, CL = 15pF(5)
PW = 66.7ns, CL = 15pF(6)
37
60
ns
40
60
ns
3
15
ns
12
25
ns
tPSK(PP)
Part-Part Skew
PW = 66.7ns, CL = 15pF(7)
30
ns
tR
tF
|CMH|
|CML|
Output Rise Time
(10% to 90%)
Output Fall Time
(90% to 10%)
Common Mode Transient
Immunity at Output High
Common Mode Transient
Immunity at Output Low
PW = 66.7ns, CL = 15pF
PW = 66.7ns, CL = 15pF
VI = VDD1, VO > 0.8VDD1,
VCM = 1000V(8)
VI = 0V, VO < 0.8V,
VCM = 1000V(8)
6.5
6.5
20
40
20
40
ns
ns
kV/µs
kV/µs
Notes:
1. No derating required.
2. 0.1µF bypass capacitor must be connected between Pin 1 and 4, and 5 and 8. The capacitors should be kept close
to the supply pins.
3. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted
together.
4. 3,750 VACRMS for 1 minute duration is equivalent to 4,500 VACRMS for 1 second duration.
5. PWD is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen for one channel
switching, while holding the other channel output at a low or high state, or while both channels are in synchronous
data transmission mode.
6. tPSK(CC) is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between the two
channels within a single device.
7. tPSK(PP) is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between any two
units from the same manufacturing date code that are operated at same case temperature, at same operating
conditions, with equal loads.
8. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of
the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient
immunity at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal,
Vcm, to assure that the output will remain low.
©2010 Fairchild Semiconductor Corporation
FOD8012 Rev. 1.0.5
4
www.fairchildsemi.com
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